linux-kernel - RE: [PATCH] x86/i8259: Work around buggy legacy PIC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 14 May 2021 16:12:01 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Thomas Gleixner' <tglx@...utronix.de>,
        Maximilian Luz <luzmaximilian@...il.com>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>
CC:     "H. Peter Anvin" <hpa@...or.com>, Sachi King <nakato@...ato.io>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: RE: [PATCH] x86/i8259: Work around buggy legacy PIC

From: Thomas Gleixner
> Sent: 14 May 2021 14:45
> 
> Max,
> 
> On Thu, May 13 2021 at 12:11, Maximilian Luz wrote:
> > And lastly, if that's any help at all: The PIC device is described in
> > ACPI in [3]. The Surface Laptop 3 also has an AMD CPU (although a prior
> > generation) and has the PIC described in the exact same way (can also be
> > found in that repository), but doesn't exhibit that behavior (and
> > doesn't show the "Using NULL legacy PIC" line). I expect there's not
> > much you can change to that definition so that's probably irrelevant
> > here.
> >
> > Again, I don't really know anything about these devices, so my guess
> > would be bad hardware revision or bad firmware revision. All I know is
> > that retrying seems to "fix" it.
> 
> That might be a a power optimization thing.
> 
> Except for older systems the PIC is not really required for IOAPiC to
> work. But there is some historical code which makes assumptions. We can
> change that, but that needs some careful thoughts.

A more interesting probe would be:
- Write some value to register 1 - the mask.
- Write 9 to register zero (selects interrupt in service register).
- Read register 0 - should be zero since we aren't in as ISR.
- Read register 1 - should get the mask back.
You can also write 8 to register 0, reads then return the pending interrupts.
Their might be pending interrupts - so that value can't be checked.

But if reads start returning the last written value you might only
have capacitors on the data bus.

The required initialisation registers are pretty fixed for the PC hardware.
But finding the values requires a bit of work.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)