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Message-Id: <20210516230551.12469-5-afaerber@suse.de>
Date: Mon, 17 May 2021 01:05:46 +0200
From: Andreas Färber <afaerber@...e.de>
To: linux-rockchip@...ts.infradead.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Andreas Färber <afaerber@...e.de>,
Rob Herring <robh+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>, devicetree@...r.kernel.org
Subject: [PATCH 4/9] arm64: dts: rockchip: Add Rockchip TB-RK1808M0
Add an initial Device Tree for Rockchip Toybrick TB-RK1808M0 mPCIe card.
Based on shipping TB-RK1808M0 DTB.
Signed-off-by: Andreas Färber <afaerber@...e.de>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk1808k-toybrick-m0.dts | 55 +++++++++++++++++++
2 files changed, 56 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk1808k-toybrick-m0.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index c3e00c0e2db7..d5a3837ccb7c 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk1808k-toybrick-m0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk1808k-toybrick-m0.dts b/arch/arm64/boot/dts/rockchip/rk1808k-toybrick-m0.dts
new file mode 100644
index 000000000000..2f8075d2391c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk1808k-toybrick-m0.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2021 Andreas Färber
+ */
+
+/dts-v1/;
+
+#include "rk1808.dtsi"
+
+/ {
+ compatible = "rockchip,tb-rk1808m0", "rockchip,rk1808";
+ model = "Rockchip Toybrick TB-RK1808M0";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vcc3v3_pcie>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&uart2 {
+ status = "okay";
+ clocks = <&xin24m>;
+ clock-names = "baudclk";
+};
--
2.31.1
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