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Message-Id: <20210518194008.2921469-1-fparent@baylibre.com>
Date: Tue, 18 May 2021 21:40:07 +0200
From: Fabien Parent <fparent@...libre.com>
To: Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Weiyi Lu <weiyi.lu@...iatek.com>
Cc: mkorpershoek@...libre.com, Fabien Parent <fparent@...libre.com>,
Matthias Brugger <mbrugger@...e.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH 1/2] dt-bindings: power: Add MT8365 power domains
Add power domains dt-bindings for MT8365.
Signed-off-by: Fabien Parent <fparent@...libre.com>
---
.../power/mediatek,power-controller.yaml | 2 ++
include/dt-bindings/power/mt8365-power.h | 20 +++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 include/dt-bindings/power/mt8365-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index f234a756c193..9a26a2cee7fb 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8192-power-controller
+ - mediatek,mt8365-power-controller
'#power-domain-cells':
const: 1
@@ -64,6 +65,7 @@ patternProperties:
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
+ "include/dt-bindings/power/mt8365-power.h" - for MT8365 type power domain.
maxItems: 1
clocks:
diff --git a/include/dt-bindings/power/mt8365-power.h b/include/dt-bindings/power/mt8365-power.h
new file mode 100644
index 000000000000..352440c4b5dd
--- /dev/null
+++ b/include/dt-bindings/power/mt8365-power.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H
+#define _DT_BINDINGS_POWER_MT8365_POWER_H
+
+#define MT8365_POWER_DOMAIN_DISP 0
+#define MT8365_POWER_DOMAIN_CONN 1
+#define MT8365_POWER_DOMAIN_MFG 2
+#define MT8365_POWER_DOMAIN_AUDIO 3
+#define MT8365_POWER_DOMAIN_CAM 4
+#define MT8365_POWER_DOMAIN_DSP 5
+#define MT8365_POWER_DOMAIN_VDEC 6
+#define MT8365_POWER_DOMAIN_VENC 7
+#define MT8365_POWER_DOMAIN_APU 8
+
+#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */
+
--
2.31.1
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