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Message-Id: <20210518082850.26048-8-o.rempel@pengutronix.de>
Date: Tue, 18 May 2021 10:28:48 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Rob Herring <robh+dt@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>
Cc: Oleksij Rempel <o.rempel@...gutronix.de>,
devicetree@...r.kernel.org, Fabio Estevam <festevam@...il.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
NXP Linux Team <linux-imx@....com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
David Jander <david@...tonic.nl>
Subject: [PATCH v1 7/9] ARM: dts: imx6qdl-vicut1: add interrupt-counter nodes
interrupt-counter is mainline now, so we can add missing counter nodes.
Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
---
arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 41 ++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
index eb25d21a2ace..b9e305774fed 100644
--- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi
@@ -40,6 +40,27 @@ comp0_out: endpoint {
};
};
+ counter-0 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter0>;
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ counter-1 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter1>;
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ counter-2 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter2>;
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -254,7 +275,7 @@ &gpio1 {
&gpio2 {
gpio-line-names =
- "", "", "", "", "", "", "", "",
+ "count0", "count1", "count2", "", "", "", "", "",
"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
"", "", "", "", "", "", "", "ON_SWITCH",
@@ -572,6 +593,24 @@ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008
>;
};
+ pinctrl_counter0: counter0grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000
+ >;
+ };
+
+ pinctrl_counter1: counter1grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000
+ >;
+ };
+
+ pinctrl_counter2: counter2grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000
+ >;
+ };
+
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
--
2.29.2
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