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Message-ID: <YKOJTtmjvxbBJOcS@hirez.programming.kicks-ass.net>
Date: Tue, 18 May 2021 11:30:54 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Like Xu <like.xu@...ux.intel.com>
Cc: Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
linux-kernel@...r.kernel.org,
Kan Liang <kan.liang@...ux.intel.com>,
Borislav Petkov <bp@...en8.de>, seanjc@...gle.com,
x86@...nel.org
Subject: Re: [PATCH v2 1/2] perf/x86: Skip checking if 0x0 MSR exists for
guest Arch LBR
On Fri, Apr 30, 2021 at 01:22:46PM +0800, Like Xu wrote:
> - Avoid checking unrelated Architecture MSR 0x0 in a simple way
I'm thinking the below is simpler still, no?
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 5272f349dca2..456aa6ffd9a1 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6250,7 +6250,8 @@ __init int intel_pmu_init(void)
> * Check all LBT MSR here.
> * Disable LBR access if any LBR MSRs can not be accessed.
> */
> - if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
> + if (x86_pmu.lbr_nr && !static_cpu_has(X86_FEATURE_ARCH_LBR) &&
> + !check_msr(x86_pmu.lbr_tos, 0x3UL))
> x86_pmu.lbr_nr = 0;
> for (i = 0; i < x86_pmu.lbr_nr; i++) {
> if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2521d03de5e0..e28892270c58 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6253,7 +6253,7 @@ __init int intel_pmu_init(void)
* Check all LBT MSR here.
* Disable LBR access if any LBR MSRs can not be accessed.
*/
- if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
+ if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
x86_pmu.lbr_nr = 0;
for (i = 0; i < x86_pmu.lbr_nr; i++) {
if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
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