linux-kernel - Re: [PATCH 2/2] dt-bindings: gpio: stp: add gphy3 and gphy4 properties

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20210518011957.GA3586154@robh.at.kernel.org>
Date:   Mon, 17 May 2021 20:19:57 -0500
From:   Rob Herring <robh@...nel.org>
To:     Aleksander Jan Bajkowski <olek2@...pl>
Cc:     linus.walleij@...aro.org, bgolaszewski@...libre.com,
        john@...ozen.org, linux-gpio@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: gpio: stp: add gphy3 and gphy4
 properties

On Thu, May 13, 2021 at 11:03:40PM +0200, Aleksander Jan Bajkowski wrote:
> The xRX300 family has 3 and the xRX330 has 4 gphs. They can also control
> some pins of the gpio cascade. This patch documents the missing properties.
> 
> Signed-off-by: Aleksander Jan Bajkowski <olek2@...pl>
> ---
>  .../devicetree/bindings/gpio/gpio-stp-xway.yaml  | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
> index a36acc98898c..beb755edf639 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
> +++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
> @@ -84,6 +84,22 @@ properties:
>      minimum: 0x0
>      maximum: 0x7
>  
> +  lantiq,phy3:
> +    description:
> +      The gphy3 core can control 3 bits of the gpio cascade. Available on
> +      the xRX300 and xRX330 family.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0x0
> +    maximum: 0x7
> +
> +  lantiq,phy4:

You could make these a pattern under patternProperties instead.

> +    description:
> +      The gphy4 core can control 3 bits of the gpio cascade. Available on
> +      the xRX330 family.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 0x0
> +    maximum: 0x7
> +
>    lantiq,rising:
>      description:
>        Use rising instead of falling edge for the shift register.
> -- 
> 2.30.2
>