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Message-ID: <YKPjwvMh3sj56sOG@vkoul-mobl.Dlink>
Date: Tue, 18 May 2021 21:26:50 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Jonathan Marek <jonathan@...ek.ca>
Cc: linux-arm-msm@...r.kernel.org, robert.foss@...aro.org,
andrey.konovalov@...aro.org, Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
On 18-05-21, 09:06, Jonathan Marek wrote:
> On 5/18/21 7:32 AM, Vinod Koul wrote:
> > > +static unsigned long
> > > +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> > > +{
> > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> > > + u32 l, frac;
> > > +
> > > + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> > > + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
> > > +
> > > + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
> > > +}
> >
> > sounds like you could use clk_trion_pll_recalc_rate() instead
> >
>
> I had this thought as well, but alpha_width in clk_trion_pll_recalc()_rate
> is 16, here ALPHA_BITWIDTH is 32, so I just copied this from downstream.
>
> I think changing pll_alpha_width() to return the right value for zonda will
> work and allow sharing the function, if you think that's a good idea?
Yes I thinking pll_alpha_width() should do the trick here
Thanks
--
~Vinod
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