[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20210519065658.GB31590@lst.de>
Date: Wed, 19 May 2021 08:56:58 +0200
From: Christoph Hellwig <hch@....de>
To: Drew Fustini <drew@...gleboard.org>
Cc: Christoph Hellwig <hch@....de>, Guo Ren <guoren@...nel.org>,
Anup Patel <anup.patel@....com>,
Palmer Dabbelt <palmerdabbelt@...gle.com>, wefu@...hat.com,
lazyparser@...il.com,
linux-riscv <linux-riscv@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-arch <linux-arch@...r.kernel.org>,
linux-sunxi@...ts.linux.dev, Guo Ren <guoren@...ux.alibaba.com>,
paul.walmsley@...ive.com
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support
On Tue, May 18, 2021 at 11:54:31PM -0700, Drew Fustini wrote:
> Isn't it a good goal for Linux to support the capabilities present in
> the SoC that a currently being fab'd?
>
> I believe the CMO group only started last year [1] so the RV64GC SoCs
> that are going into mass production this year would not have had the
> opporuntiy of utilizing any RISC-V ISA extension for handling cache
> management.
Then the vendors need to push harder. This problem has been known
for years but ignored by the vendors.
Powered by blists - more mailing lists