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Message-Id: <20210519143700.27392-18-bhupesh.sharma@linaro.org>
Date: Wed, 19 May 2021 20:07:00 +0530
From: Bhupesh Sharma <bhupesh.sharma@...aro.org>
To: linux-arm-msm@...r.kernel.org
Cc: bhupesh.sharma@...aro.org,
Thara Gopinath <thara.gopinath@...aro.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Andy Gross <agross@...nel.org>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S . Miller" <davem@...emloft.net>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Vinod Koul <vkoul@...nel.org>, dmaengine@...r.kernel.org,
linux-clk@...r.kernel.org, linux-crypto@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
bhupesh.linux@...il.com
Subject: [PATCH v3 17/17] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
Add crypto engine (CE) and CE BAM related nodes and definitions to
"sm8250.dtsi".
Cc: Thara Gopinath <thara.gopinath@...aro.org>
Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Andy Gross <agross@...nel.org>
Cc: Herbert Xu <herbert@...dor.apana.org.au>
Cc: David S. Miller <davem@...emloft.net>
Cc: Stephen Boyd <sboyd@...nel.org>
Cc: Michael Turquette <mturquette@...libre.com>
Cc: Vinod Koul <vkoul@...nel.org>
Cc: dmaengine@...r.kernel.org
Cc: linux-clk@...r.kernel.org
Cc: linux-crypto@...r.kernel.org
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: bhupesh.linux@...il.com
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
Signed-off-by: Thara Gopinath <thara.gopinath@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4c0de12aaba6..6700d609a7b8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3796,6 +3796,34 @@ cpufreq_hw: cpufreq@...91000 {
#freq-domain-cells = <1>;
};
+
+ cryptobam: dma@...4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely = <1>;
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
+
+ crypto: crypto@...a000 {
+ compatible = "qcom,sm8250-qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
};
timer {
--
2.31.1
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