linux-kernel - Re: [PATCH RFC 0/3] riscv: Add DMA

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Message-ID: <20210520054816.GA21693@lst.de>
Date:   Thu, 20 May 2021 07:48:16 +0200
From:   Christoph Hellwig <hch@....de>
To:     Guo Ren <guoren@...nel.org>
Cc:     Christoph Hellwig <hch@....de>,
        Drew Fustini <drew@...gleboard.org>,
        Anup Patel <anup.patel@....com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>, wefu@...hat.com,
        lazyparser@...il.com,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        linux-sunxi@...ts.linux.dev, Guo Ren <guoren@...ux.alibaba.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Nick Kossifidis <mick@....forth.gr>,
        Benjamin Koch <snowball@...b.de>,
        Matteo Croce <mcroce@...ux.microsoft.com>,
        Wei Fu <tekkamanninja@...il.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support

On Thu, May 20, 2021 at 09:45:45AM +0800, Guo Ren wrote:
> It's a very big MIPS smell. What's the attribute of the uncached
> window? (uncached + strong-order/ uncached + weak, most vendors still
> use AXI interconnect, how to deal with a bufferable attribute?) In
> fact, customers' drivers use different ways to deal with DMA memory in
> non-coherent SOC. Most riscv SOC vendors are from ARM, so giving them
> the same way in DMA memory is a smart choice. So using PTE attributes
> is more suitable.

I'm not saying it is a good idea.  Just that apparently this exists in
the ASICs.