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Date: Thu, 20 May 2021 11:50:29 +0900
From: Chanwoo Choi <cw00.choi@...sung.com>
To: Dmitry Osipenko <digetx@...il.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Rob Herring <robh+dt@...nel.org>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Peter Geis <pgwipeout@...il.com>,
Matt Merhar <mattmerhar@...tonmail.com>
Cc: linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v1 3/7] dt-bindings: devfreq: tegra30-actmon: Convert to
schema
On 5/11/21 6:10 AM, Dmitry Osipenko wrote:
> Convert NVIDIA Tegra ACTMON binding to schema.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> .../arm/tegra/nvidia,tegra30-actmon.txt | 57 ---------
> .../devfreq/nvidia,tegra30-actmon.yaml | 121 ++++++++++++++++++
> 2 files changed, 121 insertions(+), 57 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
> deleted file mode 100644
> index 897eedfa2bc8..000000000000
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt
> +++ /dev/null
> @@ -1,57 +0,0 @@
> -NVIDIA Tegra Activity Monitor
> -
> -The activity monitor block collects statistics about the behaviour of other
> -components in the system. This information can be used to derive the rate at
> -which the external memory needs to be clocked in order to serve all requests
> -from the monitored clients.
> -
> -Required properties:
> -- compatible: should be "nvidia,tegra<chip>-actmon"
> -- reg: offset and length of the register set for the device
> -- interrupts: standard interrupt property
> -- clocks: Must contain a phandle and clock specifier pair for each entry in
> -clock-names. See ../../clock/clock-bindings.txt for details.
> -- clock-names: Must include the following entries:
> - - actmon
> - - emc
> -- resets: Must contain an entry for each entry in reset-names. See
> -../../reset/reset.txt for details.
> -- reset-names: Must include the following entries:
> - - actmon
> -- operating-points-v2: See ../bindings/opp/opp.txt for details.
> -- interconnects: Should contain entries for memory clients sitting on
> - MC->EMC memory interconnect path.
> -- interconnect-names: Should include name of the interconnect path for each
> - interconnect entry. Consult TRM documentation for
> - information about available memory clients, see MEMORY
> - CONTROLLER section.
> -
> -For each opp entry in 'operating-points-v2' table:
> -- opp-supported-hw: bitfield indicating SoC speedo ID mask
> -- opp-peak-kBps: peak bandwidth of the memory channel
> -
> -Example:
> - dfs_opp_table: opp-table {
> - compatible = "operating-points-v2";
> -
> - opp@...50000 {
> - opp-hz = /bits/ 64 <12750000>;
> - opp-supported-hw = <0x000F>;
> - opp-peak-kBps = <51000>;
> - };
> - ...
> - };
> -
> - actmon@...0c800 {
> - compatible = "nvidia,tegra124-actmon";
> - reg = <0x0 0x6000c800 0x0 0x400>;
> - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
> - <&tegra_car TEGRA124_CLK_EMC>;
> - clock-names = "actmon", "emc";
> - resets = <&tegra_car 119>;
> - reset-names = "actmon";
> - operating-points-v2 = <&dfs_opp_table>;
> - interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
> - interconnect-names = "cpu";
> - };
> diff --git a/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml
> new file mode 100644
> index 000000000000..2a940d5d7ab4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: https://protect2.fireeye.com/v1/url?k=45c89d0a-1a53a410-45c91645-000babff24ad-23dabc3fb0c14687&q=1&e=3278a7b6-8f85-494f-a1fa-d926c45f4529&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdevfreq%2Fnvidia%2Ctegra30-actmon.yaml%23
> +$schema: https://protect2.fireeye.com/v1/url?k=f9f2037e-a6693a64-f9f38831-000babff24ad-e0e7e870e2aea6e2&q=1&e=3278a7b6-8f85-494f-a1fa-d926c45f4529&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
> +
> +title: NVIDIA Tegra30 Activity Monitor
> +
> +maintainers:
> + - Dmitry Osipenko <digetx@...il.com>
> + - Jon Hunter <jonathanh@...dia.com>
> + - Thierry Reding <thierry.reding@...il.com>
> +
> +description: |
> + The activity monitor block collects statistics about the behaviour of other
> + components in the system. This information can be used to derive the rate at
> + which the external memory needs to be clocked in order to serve all requests
> + from the monitored clients.
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra30-actmon
> + - nvidia,tegra114-actmon
> + - nvidia,tegra124-actmon
> + - nvidia,tegra210-actmon
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: actmon
> + - const: emc
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: actmon
> +
> + interrupts:
> + maxItems: 1
> +
> + interconnects:
> + minItems: 1
> + maxItems: 12
> +
> + interconnect-names:
> + minItems: 1
> + maxItems: 12
> + description:
> + Should include name of the interconnect path for each interconnect
> + entry. Consult TRM documentation for information about available
> + memory clients, see ACTIVITY MONITOR section.
> +
> + operating-points-v2:
> + description:
> + Should contain freqs and voltages and opp-supported-hw property, which
> + is a bitfield indicating SoC speedo ID mask.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - interrupts
> + - interconnects
> + - interconnect-names
> + - operating-points-v2
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/memory/tegra30-mc.h>
> +
> + mc: memory-controller@...0f000 {
> + compatible = "nvidia,tegra30-mc";
> + reg = <0x7000f000 0x400>;
> + clocks = <&clk 32>;
> + clock-names = "mc";
> +
> + interrupts = <0 77 4>;
> +
> + #iommu-cells = <1>;
> + #reset-cells = <1>;
> + #interconnect-cells = <1>;
> + };
> +
> + emc: external-memory-controller@...0f400 {
> + compatible = "nvidia,tegra30-emc";
> + reg = <0x7000f400 0x400>;
> + interrupts = <0 78 4>;
> + clocks = <&clk 57>;
> +
> + nvidia,memory-controller = <&mc>;
> + operating-points-v2 = <&dvfs_opp_table>;
> + power-domains = <&domain>;
> +
> + #interconnect-cells = <0>;
> + };
> +
> + actmon@...0c800 {
> + compatible = "nvidia,tegra30-actmon";
> + reg = <0x6000c800 0x400>;
> + interrupts = <0 45 4>;
> + clocks = <&clk 119>, <&clk 57>;
> + clock-names = "actmon", "emc";
> + resets = <&rst 119>;
> + reset-names = "actmon";
> + operating-points-v2 = <&dvfs_opp_table>;
> + interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
> + interconnect-names = "cpu-read";
> + };
>
Acked-by: Chanwoo Choi <cw00.choi@...sung.com>
After tegra SoC maintainer review this patch, I'll take it.
--
Best Regards,
Chanwoo Choi
Samsung Electronics
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