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Message-Id: <8fc49b36-256e-47ff-8834-bc60fb7a2450@www.fastmail.com>
Date:   Fri, 21 May 2021 10:36:07 +0930
From:   "Andrew Jeffery" <andrew@...id.au>
To:     "Steven Lee" <steven_lee@...eedtech.com>,
        "Rob Herring" <robh+dt@...nel.org>,
        "Joel Stanley" <joel@....id.au>,
        "Adrian Hunter" <adrian.hunter@...el.com>,
        "Ulf Hansson" <ulf.hansson@...aro.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-aspeed@...ts.ozlabs.org>,
        "open list" <linux-kernel@...r.kernel.org>,
        "moderated list:ASPEED SD/MMC DRIVER" <openbmc@...ts.ozlabs.org>,
        linux-mmc <linux-mmc@...r.kernel.org>
Cc:     "Ryan Chen" <ryan_chen@...eedtech.com>,
        "Chin-Ting Kuo" <chin-ting_kuo@...eedtech.com>,
        "Hongwei Zhang" <Hongweiz@....com>
Subject: Re: [PATCH v4 3/3] mmc: sdhci-of-aspeed: Configure the SDHCIs as specified by the devicetree.



On Thu, 20 May 2021, at 19:43, Steven Lee wrote:
> The hardware provides capability configuration registers for each SDHCI
> in the global configuration space for the SD controller. Writes to the
> global capability registers are mirrored to the capability registers in
> the associated SDHCI. Configuration of the capabilities must be written
> through the mirror registers prior to initialisation of the SDHCI.
> 
> Signed-off-by: Steven Lee <steven_lee@...eedtech.com>

Reviewed-by: Andrew Jeffery <andrew@...id.au>

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