| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 20 May 2021 20:20:16 -0500
From: Rob Herring <robh@...nel.org>
To: Fabien Parent <fparent@...libre.com>
Cc: Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Lee Jones <lee.jones@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
mkorpershoek@...libre.com, linux-pwm@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] dt-bindings: pwm: pwm-mtk-disp: convert to YAML
schema
On Tue, May 18, 2021 at 07:54:19PM +0200, Fabien Parent wrote:
> Convert the dt-binding documentation for pwm-mtk-disp to YAML.
>
> Signed-off-by: Fabien Parent <fparent@...libre.com>
> ---
> .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ----------
> .../devicetree/bindings/pwm/pwm-mtk-disp.yaml | 83 +++++++++++++++++++
> 2 files changed, 83 insertions(+), 44 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
> deleted file mode 100644
> index 902b271891ae..000000000000
> --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -MediaTek display PWM controller
> -
> -Required properties:
> - - compatible: should be "mediatek,<name>-disp-pwm":
> - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
> - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
> - - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
> - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
> - - reg: physical base address and length of the controller's registers.
> - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
> - the cell format.
> - - clocks: phandle and clock specifier of the PWM reference clock.
> - - clock-names: must contain the following:
> - - "main": clock used to generate PWM signals.
> - - "mm": sync signals from the modules of mmsys.
> - - pinctrl-names: Must contain a "default" entry.
> - - pinctrl-0: One property must exist for each entry in pinctrl-names.
> - See pinctrl/pinctrl-bindings.txt for details of the property values.
> -
> -Example:
> - pwm0: pwm@...1e000 {
> - compatible = "mediatek,mt8173-disp-pwm",
> - "mediatek,mt6595-disp-pwm";
> - reg = <0 0x1401e000 0 0x1000>;
> - #pwm-cells = <2>;
> - clocks = <&mmsys CLK_MM_DISP_PWM026M>,
> - <&mmsys CLK_MM_DISP_PWM0MM>;
> - clock-names = "main", "mm";
> - pinctrl-names = "default";
> - pinctrl-0 = <&disp_pwm0_pins>;
> - };
> -
> - backlight_lcd: backlight_lcd {
> - compatible = "pwm-backlight";
> - pwms = <&pwm0 0 1000000>;
> - brightness-levels = <
> - 0 16 32 48 64 80 96 112
> - 128 144 160 176 192 208 224 240
> - 255
> - >;
> - default-brightness-level = <9>;
> - power-supply = <&mt6397_vio18_reg>;
> - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
> - };
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.yaml b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.yaml
> new file mode 100644
> index 000000000000..0f016c81cd53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/pwm/pwm-mtk-disp.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek display PWM controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@...il.com>
> + - Lee Jones <lee.jones@...aro.org>
> + - Matthias Brugger <matthias.bgg@...il.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt2701-disp-pwm
> + - mediatek,mt6595-disp-pwm
> + - mediatek,mt8173-disp-pwm
> + - items:
> + - const: mediatek,mt8167-disp-pwm
> + - const: mediatek,mt8173-disp-pwm
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: clock used to generate PWM signals
> + - description: sync signal from the mmsys module
> +
> + clock-names:
> + items:
> + - const: main
> + - const: mm
> +
> + "#pwm-cells":
> + const: 2
> +
> + power-domains:
> + description:
> + List of phandles and PM domain specifiers, as defined by bindings of the
> + PM domain provider (see also ../power_domain.txt).
Don't need to define what the common property is. You need to say how
many.
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/gpio/gpio.h>
> + pwm0: pwm@...1e000 {
> + compatible = "mediatek,mt8173-disp-pwm";
> + reg = <0x1401e000 0x1000>;
> + #pwm-cells = <2>;
> + clocks = <&mmsys CLK_MM_DISP_PWM026M>,
> + <&mmsys CLK_MM_DISP_PWM0MM>;
> + clock-names = "main", "mm";
> + pinctrl-names = "default";
> + pinctrl-0 = <&disp_pwm0_pins>;
> + };
> +
> + backlight_lcd: backlight_lcd {
> + compatible = "pwm-backlight";
> + pwms = <&pwm0 0 1000000>;
> + brightness-levels = <
> + 0 16 32 48 64 80 96 112
> + 128 144 160 176 192 208 224 240
> + 255
> + >;
> + default-brightness-level = <9>;
> + power-supply = <&mt6397_vio18_reg>;
> + enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
> + };
> --
> 2.31.1
>
Powered by blists - more mailing lists