linux-kernel - Re: [PATCH] drm/amdgpu: Fix inconsistent indenting

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Date:   Fri, 21 May 2021 15:35:51 +0200
From:   Christian König <ckoenig.leichtzumerken@...il.com>
To:     Jiapeng Chong <jiapeng.chong@...ux.alibaba.com>,
        alexander.deucher@....com
Cc:     airlied@...ux.ie, Xinhui.Pan@....com, linux-kernel@...r.kernel.org,
        amd-gfx@...ts.freedesktop.org, sumit.semwal@...aro.org,
        linaro-mm-sig@...ts.linaro.org, dri-devel@...ts.freedesktop.org,
        daniel@...ll.ch, christian.koenig@....com,
        linux-media@...r.kernel.org
Subject: Re: [PATCH] drm/amdgpu: Fix inconsistent indenting

Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
>
> Reported-by: Abaci Robot <abaci@...ux.alibaba.com>
> Signed-off-by: Jiapeng Chong <jiapeng.chong@...ux.alibaba.com>

Reviewed-by: Christian König <christian.koenig@....com>

> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-------
>   1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 75d7310..c45e1b0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
>    */
>   static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
>   {
> -    uint32_t gcr_cntl =
> -		    SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> -			SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> -			SDMA_GCR_GLI_INV(1);
> +	uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> +			    SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> +			    SDMA_GCR_GLI_INV(1);
>   
>   	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
>   	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
>   	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
>   	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> -			SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> +			  SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
>   	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> -			SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> +			  SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
>   	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> -			SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> +			  SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
>   }
>   
>   /**