linux-kernel - Re: [PATCH v2 12/14] dt-bindings: soc: tegra-pmc: Document core power domain

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Message-ID: <CAPDyKFqp1TN1JUa9R3c2VZ3tyD+FRVhYEVc1rw76Uq5r8n9dWw@mail.gmail.com>
Date:   Mon, 24 May 2021 19:02:58 +0200
From:   Ulf Hansson <ulf.hansson@...aro.org>
To:     Dmitry Osipenko <digetx@...il.com>
Cc:     Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Michał Mirosław <mirq-linux@...e.qmqm.pl>,
        Nikola Milosavljević <mnidza@...look.com>,
        Peter Geis <pgwipeout@...il.com>,
        Nicolas Chauvet <kwizart@...il.com>,
        Viresh Kumar <vireshk@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Matt Merhar <mattmerhar@...tonmail.com>,
        Paul Fertser <fercerpav@...il.com>,
        Mark Brown <broonie@...nel.org>,
        Liam Girdwood <lgirdwood@...il.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Mikko Perttunen <mperttunen@...dia.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-tegra <linux-tegra@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>,
        Linux PM <linux-pm@...r.kernel.org>,
        Nathan Chancellor <nathan@...nel.org>,
        linux-clk <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v2 12/14] dt-bindings: soc: tegra-pmc: Document core power domain

On Mon, 24 May 2021 at 01:13, Dmitry Osipenko <digetx@...il.com> wrote:
>
> All NVIDIA Tegra SoCs have a core power domain where majority of hardware
> blocks reside. Document the new core power domain properties.
>
> Reviewed-by: Rob Herring <robh@...nel.org>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>

Reviewed-by: Ulf Hansson <ulf.hansson@...aro.org>

Kind regards
Uffe


> ---
>  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> index 43fd2f8927d0..0afec83cc723 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> @@ -301,6 +301,33 @@ patternProperties:
>
>      additionalProperties: false
>
> +  core-domain:
> +    type: object
> +    description: |
> +      The vast majority of hardware blocks of Tegra SoC belong to a
> +      Core power domain, which has a dedicated voltage rail that powers
> +      the blocks.
> +
> +    properties:
> +      operating-points-v2:
> +        description:
> +          Should contain level, voltages and opp-supported-hw property.
> +          The supported-hw is a bitfield indicating SoC speedo or process
> +          ID mask.
> +
> +      "#power-domain-cells":
> +        const: 0
> +
> +    required:
> +      - operating-points-v2
> +      - "#power-domain-cells"
> +
> +    additionalProperties: false
> +
> +  core-supply:
> +    description:
> +      Phandle to voltage regulator connected to the SoC Core power rail.
> +
>  required:
>    - compatible
>    - reg
> @@ -325,6 +352,7 @@ examples:
>      tegra_pmc: pmc@...0e400 {
>                compatible = "nvidia,tegra210-pmc";
>                reg = <0x7000e400 0x400>;
> +              core-supply = <&regulator>;
>                clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
>                clock-names = "pclk", "clk32k_in";
>                #clock-cells = <1>;
> @@ -338,17 +366,24 @@ examples:
>                nvidia,core-power-req-active-high;
>                nvidia,sys-clock-req-active-high;
>
> +              pd_core: core-domain {
> +                      operating-points-v2 = <&core_opp_table>;
> +                      #power-domain-cells = <0>;
> +              };
> +
>                powergates {
>                      pd_audio: aud {
>                              clocks = <&tegra_car TEGRA210_CLK_APE>,
>                                       <&tegra_car TEGRA210_CLK_APB2APE>;
>                              resets = <&tegra_car 198>;
> +                            power-domains = <&pd_core>;
>                              #power-domain-cells = <0>;
>                      };
>
>                      pd_xusbss: xusba {
>                              clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
>                              resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
> +                            power-domains = <&pd_core>;
>                              #power-domain-cells = <0>;
>                      };
>                };
> --
> 2.30.2
>