linux-kernel - Re: [PATCH v5 0/4] mmc: sdhci-of-aspeed: Support toggling SD bus signal

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Message-Id: <e95c5263-d50f-4316-bb93-e14449559b1b@www.fastmail.com>
Date:   Wed, 26 May 2021 08:29:41 +0930
From:   "Andrew Jeffery" <andrew@...id.au>
To:     "Joel Stanley" <joel@....id.au>,
        "Steven Lee" <steven_lee@...eedtech.com>
Cc:     "Rob Herring" <robh+dt@...nel.org>,
        "Adrian Hunter" <adrian.hunter@...el.com>,
        "Ulf Hansson" <ulf.hansson@...aro.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-aspeed@...ts.ozlabs.org>,
        "open list" <linux-kernel@...r.kernel.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        "moderated list:ASPEED SD/MMC DRIVER" <openbmc@...ts.ozlabs.org>,
        "Hongwei Zhang" <Hongweiz@....com>,
        "Ryan Chen" <ryan_chen@...eedtech.com>,
        "Chin-Ting Kuo" <chin-ting_kuo@...eedtech.com>
Subject: Re: [PATCH v5 0/4] mmc: sdhci-of-aspeed: Support toggling SD bus signal



On Tue, 25 May 2021, at 22:26, Joel Stanley wrote:
> On Tue, 25 May 2021 at 09:48, Steven Lee <steven_lee@...eedtech.com> wrote:
> >
> > The 05/25/2021 15:55, Joel Stanley wrote:
> > > When I was testing on my A2 EVB I saw this:
> > >
> > > [    1.436219] sdhci-aspeed 1e750100.sdhci: Requested out of range
> > > phase tap 192 for 9 degrees of phase compensation at 1562500Hz,
> > > clamping to tap 15
> > > [    1.450913] sdhci-aspeed 1e750100.sdhci: Requested out of range
> > > phase tap 963 for 45 degrees of phase compensation at 1562500Hz,
> > > clamping to tap 15
> > >
> > > Do you know what is happening there?
> > >
> >
> > Per MMC spec, eMMC bus speed is set as legacy mode(0~26MHz) at startup of
> > eMMC initializtion flow. Clock phase calculation is triggered in set_clock()
> > and it calculates taps based on phase_deg(<9>, <225>) in the dts file and the
> > current speed(1562500Hz), which causes the warning message you mentioned.
> > As the phase_deg in the dts file should be calculated with 100MHz.
> >
> > https://lkml.org/lkml/2021/5/24/95
> >
> > But after some initialization flow, eMMC bus speed will be set to
> > correct speed(100MHz).
> > Clock phase calculation will be triggered again to get correct taps.
> 
> Thanks for the explanation. I added another debug print and I can see
> it doing what you describe:
> 
> [    1.465904] sdhci-aspeed 1e750100.sdhci: Requested out of range
> phase tap 192 for 9 degrees of phase compensation at 1562500Hz,
> clamping to tap 15
> [    1.480598] sdhci-aspeed 1e750100.sdhci: rate 1562500 phase 9 tap 15
> [    1.490316] sdhci-aspeed 1e750100.sdhci: Requested out of range
> phase tap 963 for 45 degrees of phase compensation at 1562500Hz,
> clamping to tap 15
> [    1.505077] sdhci-aspeed 1e750100.sdhci: rate 1562500 phase 45 tap 15
> [    1.515059] sdhci-aspeed 1e750100.sdhci: rate 100000000 phase 9 tap 3
> [    1.524886] sdhci-aspeed 1e750100.sdhci: rate 100000000 phase 45 tap 15
> [    1.534904] sdhci-aspeed 1e750100.sdhci: rate 100000000 phase 9 tap 3
> [    1.544713] sdhci-aspeed 1e750100.sdhci: rate 100000000 phase 45 tap 15
> 
> We should change the "out of range" message to be dev_dbg, as it is
> expected on a normal boot.

I would think the issue is rather that we shouldn't be applying a phase 
correction for a bus speed that isn't what the correction was specified 
for.

Let me look at this a bit further.

Andrew