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Message-ID: <YK0FFJOOalQZKl1q@sirena.org.uk>
Date: Tue, 25 May 2021 15:09:24 +0100
From: Mark Brown <broonie@...nel.org>
To: Richard Fitzgerald <rf@...nsource.cirrus.com>
Cc: Lucas Tanure <tanureal@...nsource.cirrus.com>,
James Schulman <james.schulman@...rus.com>,
David Rhodes <david.rhodes@...rus.com>,
Liam Girdwood <lgirdwood@...il.com>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>, alsa-devel@...a-project.org,
patches@...nsource.cirrus.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/4] ASoC: cs42l42: Fix 1536000 Bit Clock instability
On Tue, May 25, 2021 at 10:12:39AM +0100, Richard Fitzgerald wrote:
> Reviewed-by: Richard Fitzgerald <rf@...nsource.cirrus.com>
>
> On 25/05/2021 10:08, Lucas Tanure wrote:
> > The 16 Bits, 2 channels, 48K sample rate use case needs
> > to configure a safer pll_divout during the start of PLL
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