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Message-Id: <20210525152225.154302-2-knaerzche@gmail.com>
Date: Tue, 25 May 2021 17:22:16 +0200
From: Alex Bee <knaerzche@...il.com>
To: Ezequiel Garcia <ezequiel@...labora.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Philipp Zabel <p.zabel@...gutronix.de>,
Lee Jones <lee.jones@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org
Cc: Alex Bee <knaerzche@...il.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-staging@...ts.linux.dev
Subject: [PATCH 01/10] ARM: dts: rockchip: add power controller for RK322x
Add the power controller node and the correspondending qos nodes for
RK322x.
Also add the power-domain property to the nodes that are already
present.
Signed-off-by: Alex Bee <knaerzche@...il.com>
---
arch/arm/boot/dts/rk322x.dtsi | 112 ++++++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 5774bc309eb7..c8095ede7d7a 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/rk3228-power.h>
/ {
#address-cells = <1>;
@@ -240,6 +241,65 @@ u2phy1_host: host-port {
status = "disabled";
};
};
+
+ power: power-controller {
+ compatible = "rockchip,rk3228-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@...228_PD_VIO {
+ reg = <RK3228_PD_VIO>;
+ clocks = <&cru ACLK_HDCP>,
+ <&cru SCLK_HDCP>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru SCLK_RGA>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_iep>,
+ <&qos_rga_r>,
+ <&qos_rga_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@...228_PD_VOP {
+ reg = <RK3228_PD_VOP>;
+ clocks =<&cru ACLK_VOP>,
+ <&cru DCLK_VOP>,
+ <&cru HCLK_VOP>;
+ pm_qos = <&qos_vop>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@...228_PD_VPU {
+ reg = <RK3228_PD_VPU>;
+ clocks = <&cru ACLK_VPU>,
+ <&cru HCLK_VPU>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@...228_PD_RKVDEC {
+ reg = <RK3228_PD_RKVDEC>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ pm_qos = <&qos_rkvdec_r>,
+ <&qos_rkvdec_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@...228_PD_GPU {
+ reg = <RK3228_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ };
+
+ };
+
};
uart0: serial@...10000 {
@@ -546,6 +606,7 @@ gpu: gpu@...00000 {
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3228_PD_GPU>;
resets = <&cru SRST_GPU_A>;
status = "disabled";
};
@@ -556,6 +617,7 @@ vpu_mmu: iommu@...20800 {
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -566,6 +628,7 @@ vdec_mmu: iommu@...30480 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_RKVDEC>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -576,6 +639,7 @@ vop: vop@...50000 {
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = <&power RK3228_PD_VOP>;
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
@@ -598,6 +662,7 @@ vop_mmu: iommu@...53f00 {
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VOP>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -608,6 +673,7 @@ rga: rga@...60000 {
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3228_PD_VIO>;
resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
reset-names = "core", "axi", "ahb";
};
@@ -618,6 +684,7 @@ iep_mmu: iommu@...70800 {
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -792,6 +859,51 @@ gmac: ethernet@...00000 {
status = "disabled";
};
+ qos_iep: qos@...30080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030080 0x20>;
+ };
+
+ qos_rga_w: qos@...30100 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030100 0x20>;
+ };
+
+ qos_hdcp: qos@...30180 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030180 0x20>;
+ };
+
+ qos_rga_r: qos@...30200 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030200 0x20>;
+ };
+
+ qos_vpu: qos@...40000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31040000 0x20>;
+ };
+
+ qos_gpu: qos@...50000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31050000 0x20>;
+ };
+
+ qos_vop: qos@...60000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31060000 0x20>;
+ };
+
+ qos_rkvdec_r: qos@...70000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070000 0x20>;
+ };
+
+ qos_rkvdec_w: qos@...70080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070080 0x20>;
+ };
+
gic: interrupt-controller@...10000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.27.0
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