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Date: Thu, 27 May 2021 09:22:51 +0900
From: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
To: Rob Herring <robh+dt@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
PCI <linux-pci@...r.kernel.org>,
Punit Agrawal <punit1.agrawal@...hiba.co.jp>,
yuji2.ishikawa@...hiba.co.jp,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/3] dt-bindings: pci: Add DT binding for Toshiba
Visconti PCIe controller
On Wed, May 26, 2021 at 11:33:35AM -0500, Rob Herring wrote:
> On Mon, May 24, 2021 at 1:30 AM Nobuhiro Iwamatsu
> <nobuhiro1.iwamatsu@...hiba.co.jp> wrote:
> >
> > This commit adds the Device Tree binding documentation that allows
> > to describe the PCIe controller found in Toshiba Visconti SoCs.
> >
> > v1 -> v2:
> > - Remove white space.
> > - Drop num-viewport and bus-range from required.
> > - Drop status line from example.
> > - Drop bus-range from required.
> > - Removed lines defined in pci-bus.yaml from required.
> >
> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
> > ---
> > .../bindings/pci/toshiba,visconti-pcie.yaml | 110 ++++++++++++++++++
> > 1 file changed, 110 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
>
> Please resend to DT list. Otherwise, automated checks don't run
OK, I will resent to DT list.
> (though I'm sure you ran 'make dt_binding_check' already, right?).
Yes, I ran it enerytime.
> >
> > diff --git a/Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml b/Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
> > new file mode 100644
> > index 000000000000..d47a4a3c49e3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
> > @@ -0,0 +1,110 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Toshiba Visconti5 SoC PCIe Host Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
> > +
> > +description: |+
> > + Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP.
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: toshiba,visconti-pcie
> > +
> > + reg:
> > + items:
> > + - description: Data Bus Interface (DBI) registers.
> > + - description: PCIe configuration space region.
> > + - description: Visconti specific additional registers.
> > + - description: Visconti specific SMU registers
> > + - description: Visconti specific memory protection unit registers (MPU)
> > +
> > + reg-names:
> > + items:
> > + - const: dbi
> > + - const: config
> > + - const: ulreg
> > + - const: smu
> > + - const: mpu
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: PCIe reference clock
> > + - description: PCIe system clock
> > + - description: Auxiliary clock
> > +
> > + clock-names:
> > + items:
> > + - const: pcie_refclk
>
> Just 'refclk'. Though 'clk' is redundant too. I'd go with 'ref',
> 'aux', and 'core'.
>
Ok, I will update.
> > + - const: sysclk
> > + - const: auxclk
> > +
> > + num-lanes:
> > + const: 2
> > +
> > +required:
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - "#interrupt-cells"
> > + - interrupt-map
> > + - interrupt-map-mask
> > + - num-lanes
> > + - clocks
> > + - clock-names
> > + - max-link-speed
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie: pcie@...00000 {
> > + compatible = "toshiba,visconti-pcie";
> > + reg = <0x0 0x28400000 0x0 0x00400000>,
> > + <0x0 0x70000000 0x0 0x10000000>,
> > + <0x0 0x28050000 0x0 0x00010000>,
> > + <0x0 0x24200000 0x0 0x00002000>,
> > + <0x0 0x24162000 0x0 0x00001000>;
> > + reg-names = "dbi", "config", "ulreg", "smu", "mpu";
> > + device_type = "pci";
> > + bus-range = <0x00 0xff>;
> > + num-lanes = <2>;
> > + num-viewport = <8>;
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>,
> > + <0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
> > + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "intr";
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map =
> > + <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
> > + clock-names = "pcie_refclk", "sysclk", "auxclk";
> > + max-link-speed = <2>;
> > + };
> > + };
> > +...
> > --
> > 2.31.1
> >
>
Best regards,
Nobuhiro
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