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Message-Id: <20210527063906.18592-1-shruthi.sanil@intel.com>
Date: Thu, 27 May 2021 12:09:04 +0530
From: shruthi.sanil@...el.com
To: daniel.lezcano@...aro.org, tglx@...utronix.de, robh+dt@...nel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Cc: andriy.shevchenko@...ux.intel.com, kris.pan@...ux.intel.com,
mgross@...ux.intel.com, srikanth.thokala@...el.com,
lakshmi.bai.raja.subramanian@...el.com,
mallikarjunappa.sangannavar@...el.com, shruthi.sanil@...el.com
Subject: [PATCH v3 0/2] Add the driver for Intel Keem Bay SoC timer block
From: Shruthi Sanil <shruthi.sanil@...el.com>
The timer block supports 1 64-bit free running counter
and 8 32-bit general purpose timers.
Patch 1 holds the device tree binding documentation.
Patch 2 holds the device driver.
This driver is tested on the Keem Bay evaluation module board.
I would like to inform that, I would be taking the ownership
of this patch series from this version.
Changes since v2:
- Add multi timer support.
- Update in the device tree binding to support multi timers.
- Code optimization.
Changes since v1:
- Add support for KEEMBAY_TIMER to get selected through Kconfig.platforms.
- Add CLOCK_EVT_FEAT_DYNIRQ as part of clockevent feature.
- Avoid overlapping reg regions across 2 device nodes.
- Simplify 2 device nodes as 1 because both are from same IP block.
- Adapt the driver code according to the new simplified devicetree.
Shruthi Sanil (2):
dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
clocksource: Add Intel Keem Bay timer support
.../bindings/timer/intel,keembay-timer.yaml | 180 +++++++++++++
MAINTAINERS | 5 +
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keembay.c | 255 ++++++++++++++++++
5 files changed, 452 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
create mode 100644 drivers/clocksource/timer-keembay.c
base-commit: ad9f25d338605d26acedcaf3ba5fab5ca26f1c10
--
2.17.1
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