linux-kernel - Re: [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMuHMdXGVshtJ_YzGHtzhvXk5DZwcWbbM18E5Yo5rTMCrbO3Fw@mail.gmail.com>
Date:   Thu, 27 May 2021 13:47:15 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Rob Herring <robh+dt@...nel.org>,
        Magnus Damm <magnus.damm@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Jiri Slaby <jirislaby@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new
 RZ/G2{L,LC} SoC's

Hi Prabhakar,

On Fri, May 21, 2021 at 7:21 PM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
> On Fri, May 21, 2021 at 2:25 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > > Add ARCH_R9A07G044{L,LC} as a configuration symbol for the new Renesas
> > > RZ/G2{L,LC} SoC's.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/soc/renesas/Kconfig
> > > +++ b/drivers/soc/renesas/Kconfig
> > > @@ -279,6 +279,16 @@ config ARCH_R8A774B1
> > >         help
> > >           This enables support for the Renesas RZ/G2N SoC.
> > >
> > > +config ARCH_R9A07G044L
> > > +       bool "ARM64 Platform support for RZ/G2L SoC"
> >
> > Please drop the "SoC", for consistency with other entries.
> >
> Oops will do that.
>
> > > +       help
> > > +         This enables support for the Renesas RZ/G2L SoC.
> > > +
> > > +config ARCH_R9A07G044LC
> > > +       bool "ARM64 Platform support for RZ/G2LC SoC"
> >
> > Likewise.
> >
> will do.
>
> > > +       help
> > > +         This enables support for the Renesas RZ/G2LC SoC.
> > > +
> > >  endif # ARM64
> >
> > Given LSI DEVID is the same, do we need both, or can we do with a
> > single ARCH_R9A07G044?
> >
> The reason behind adding separate configs was in case if we wanted to
> just build an image for RZ/G2L and not RZ/G2LC this would increase
> image size and also build unneeded dtb's.

How would it increase image size? I understand clock and pin control
are the same blocks.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds