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Message-ID: <e1ad087e-a951-4128-923e-867a8b38ecec@hygon.cn>
Date:   Mon, 31 May 2021 22:56:50 +0800
From:   Pu Wen <puwen@...on.cn>
To:     Joerg Roedel <jroedel@...e.de>
CC:     Sean Christopherson <seanjc@...gle.com>, <x86@...nel.org>,
        <joro@...tes.org>, <thomas.lendacky@....com>,
        <dave.hansen@...ux.intel.com>, <peterz@...radead.org>,
        <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...e.de>,
        <hpa@...or.com>, <sashal@...nel.org>, <gregkh@...uxfoundation.org>,
        <linux-kernel@...r.kernel.org>, <kvm@...r.kernel.org>,
        <stable@...r.kernel.org>
Subject: Re: [PATCH] x86/sev: Check whether SEV or SME is supported first

On 2021/5/31 17:37, Joerg Roedel wrote:
> On Thu, May 27, 2021 at 11:08:32PM +0800, Pu Wen wrote:
>> Reading MSR_AMD64_SEV which is not implemented on Hygon Dhyana CPU will cause
>> the kernel reboot, and native_read_msr_safe() has no help.
> 
> The reason for the reboot is that there is no #GP or #DF handler set up
> when this MSR is read, so its propagated to a shutdown event. But there
> is an IDT already, so you can set up early and #GP handler to fix the
> reboot.

Thanks for your suggestion, I'll try to set up early #GP handler to fix
the problem.

-- 
Regards,
Pu Wen

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