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Message-ID: <0cd72191-e195-eae3-f741-a3c3e38298cc@microchip.com>
Date: Mon, 31 May 2021 08:00:58 +0000
From: <Tudor.Ambarus@...rochip.com>
To: <michael@...le.cc>, <linux-mtd@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <p.yadav@...com>, <miquel.raynal@...tlin.com>, <richard@....at>,
<vigneshr@...com>
Subject: Re: [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security
registers in 4 byte mode
On 5/20/21 6:58 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The security registers either take a 3 byte or a 4 byte address offset,
> depending on the address mode of the flash. Thus just leave the
> nor->addr_width as is.
>
> Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes")
> Signed-off-by: Michael Walle <michael@...le.cc>
> ---
> drivers/mtd/spi-nor/otp.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
> index 61036c716abb..91a4c510ed51 100644
> --- a/drivers/mtd/spi-nor/otp.c
> +++ b/drivers/mtd/spi-nor/otp.c
> @@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf)
> rdesc = nor->dirmap.rdesc;
>
> nor->read_opcode = SPINOR_OP_RSECR;
> - nor->addr_width = 3;
> nor->read_dummy = 8;
> nor->read_proto = SNOR_PROTO_1_1_1;
> nor->dirmap.rdesc = NULL;
> @@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
> wdesc = nor->dirmap.wdesc;
>
> nor->program_opcode = SPINOR_OP_PSECR;
> - nor->addr_width = 3;
> nor->write_proto = SNOR_PROTO_1_1_1;
> nor->dirmap.wdesc = NULL;
>
I'm not convinced that this is good. I see that winbond uses 3 bytes addr with for the
SPINOR_OP_RSECR and SPINOR_OP_PSECR, even for bigger flashes:
https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25Q256JW
Micheal, can you double check?
ta
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