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Message-Id: <20210601090408.22025-5-qiangqing.zhang@nxp.com>
Date: Tue, 1 Jun 2021 17:04:08 +0800
From: Joakim Zhang <qiangqing.zhang@....com>
To: davem@...emloft.net, kuba@...nel.org, robh+dt@...nel.org,
andrew@...n.ch, hkallweit1@...il.com, linux@...linux.org.uk,
f.fainelli@...il.com
Cc: linux-imx@....com, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH net-next 4/4] net: phy: realtek: add delay to fix RXC generation issue
PHY will delay about 11.5ms to generate RXC clock when switching from
power down to normal operation. Read/write registers would also cause RXC
become unstable and stop for a while during this process. Realtek engineer
suggests 15ms or more delay can workaround this issue. All these
statistics are collected with ALDPS mode disabled, so use RTL821X_ALDPS_DISABLE
quirk check.
Signed-off-by: Joakim Zhang <qiangqing.zhang@....com>
---
drivers/net/phy/realtek.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 90e3a8cbfc2f..b45deda839f8 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -408,6 +408,22 @@ static int rtl8211f_config_init(struct phy_device *phydev)
return genphy_soft_reset(phydev);
}
+static int rtl821x_resume(struct phy_device *phydev)
+{
+ struct rtl821x_priv *priv = phydev->priv;
+ int ret;
+
+ ret = genphy_resume(phydev);
+ if (ret < 0)
+ return ret;
+
+ /* delay time is collected with ALDPS mode disabled. */
+ if (priv->quirks & RTL821X_ALDPS_DISABLE_FEATURE)
+ msleep(20);
+
+ return 0;
+}
+
static int rtl8211e_config_init(struct phy_device *phydev)
{
int ret = 0, oldpage;
@@ -904,7 +920,7 @@ static struct phy_driver realtek_drvs[] = {
.config_intr = &rtl8211f_config_intr,
.handle_interrupt = rtl8211f_handle_interrupt,
.suspend = genphy_suspend,
- .resume = genphy_resume,
+ .resume = rtl821x_resume,
.read_page = rtl821x_read_page,
.write_page = rtl821x_write_page,
}, {
--
2.17.1
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