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Message-ID: <20210601114154.3163327-1-yangyingliang@huawei.com>
Date: Tue, 1 Jun 2021 19:41:54 +0800
From: Yang Yingliang <yangyingliang@...wei.com>
To: <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<linux-clk@...r.kernel.org>
CC: <paul.walmsley@...ive.com>, <mturquette@...libre.com>,
<sboyd@...nel.org>
Subject: [PATCH -next] clk: analogbits: fix doc warning in wrpll-cln28hpc.c
Fix the following make W=1 warning:
drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting prototype for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead
Signed-off-by: Yang Yingliang <yangyingliang@...wei.com>
---
drivers/clk/analogbits/wrpll-cln28hpc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index 7c64ea52a8d5..09ca82356399 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -202,7 +202,7 @@ static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
}
/**
- * wrpll_configure() - compute PLL configuration for a target rate
+ * wrpll_configure_for_rate() - compute PLL configuration for a target rate
* @c: ptr to a struct wrpll_cfg record to write into
* @target_rate: target PLL output clock rate (post-Q-divider)
* @parent_rate: PLL input refclk rate (pre-R-divider)
--
2.25.1
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