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Message-ID: <SN6PR11MB31337B2646C812ED2B88DFA2F13C9@SN6PR11MB3133.namprd11.prod.outlook.com>
Date: Thu, 3 Jun 2021 11:31:32 +0000
From: "Sanil, Shruthi" <shruthi.sanil@...el.com>
To: Rob Herring <robh@...nel.org>
CC: "daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"andriy.shevchenko@...ux.intel.com"
<andriy.shevchenko@...ux.intel.com>,
"kris.pan@...ux.intel.com" <kris.pan@...ux.intel.com>,
"mgross@...ux.intel.com" <mgross@...ux.intel.com>,
"Thokala, Srikanth" <srikanth.thokala@...el.com>,
"Raja Subramanian, Lakshmi Bai"
<lakshmi.bai.raja.subramanian@...el.com>,
"Sangannavar, Mallikarjunappa"
<mallikarjunappa.sangannavar@...el.com>
Subject: RE: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem
Bay SoC Timer
Hi Rob,
> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: Thursday, June 3, 2021 12:52 AM
> To: Sanil, Shruthi <shruthi.sanil@...el.com>
> Cc: daniel.lezcano@...aro.org; tglx@...utronix.de; linux-
> kernel@...r.kernel.org; devicetree@...r.kernel.org;
> andriy.shevchenko@...ux.intel.com; kris.pan@...ux.intel.com;
> mgross@...ux.intel.com; Thokala, Srikanth <srikanth.thokala@...el.com>;
> Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@...el.com>;
> Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@...el.com>
> Subject: Re: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem
> Bay SoC Timer
>
> On Thu, May 27, 2021 at 12:09:05PM +0530, shruthi.sanil@...el.com wrote:
> > From: Shruthi Sanil <shruthi.sanil@...el.com>
> >
> > Add Device Tree bindings for the Timer IP, which can be used as
> > clocksource and clockevent device in the Intel Keem Bay SoC.
> >
> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@...el.com>
> > Signed-off-by: Shruthi Sanil <shruthi.sanil@...el.com>
> > ---
> > .../bindings/timer/intel,keembay-timer.yaml | 180 ++++++++++++++++++
> > 1 file changed, 180 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> > new file mode 100644
> > index 000000000000..e0152e19208f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/intel,keembay-
> timer.yaml
> > @@ -0,0 +1,180 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Intel Keem Bay SoC Timers
> > +
> > +maintainers:
> > + - Shruthi Sanil <shruthi.sanil@...el.com>
> > +
> > +description: |
> > + The Intel Keem Bay timer driver supports clocksource and clockevent
> > + features for the timer IP used in Intel Keembay SoC.
> > + The timer block supports 1 free running counter and 8 timers.
> > + The free running counter can be used as a clocksouce and
> > + the timers can be used as clockevent. Each timer is capable of
> > + generating inividual interrupt.
> > + Both the features are enabled through the timer general config register.
> > +
> > + The parent node represents the common general configuration details
> > + and the child nodes represents the counter and timers.
> > +
> > +properties:
>
> There's no compatible, so this schema will never be applied. You need a
> compatible to identify what the block is.
>
This is a parent block that has the common configuration register address defined which we would need during the initialization of the child nodes.
This block in itself is not doing anything. We have this because, we have a common register that is required to be accessed during all the timers and counter initialization.
The child nodes have the compatible string.
I have validated this on the HW and see that the timer probes are being called and the timers are functional as expected.
Please suggest if there is a better way to handle this scenario.
> > + reg:
> > + description: General configuration register address and length.
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
>
> Not really any reason for 64-bits of address space in the child nodes.
> Use a non-empty ranges.
OK, I'll remove it.
>
> > +
> > + ranges: true
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - "#address-cells"
> > + - "#size-cells"
> > + - ranges
> > +
> > +patternProperties:
> > + "^counter@[0-9a-f]+$":
> > + type: object
> > + description: Properties for Intel Keem Bay counter
> > +
> > + properties:
> > + compatible:
> > + enum:
> > + - intel,keembay-counter
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > + "^timer@[0-9a-f]+$":
> > + type: object
> > + description: Properties for Intel Keem Bay timer
> > +
> > + properties:
> > + compatible:
> > + enum:
> > + - intel,keembay-timer
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #define KEEM_BAY_A53_TIM
> > +
> > + soc {
> > + #address-cells = <0x2>;
> > + #size-cells = <0x2>;
> > +
> > + gpt@...31000 {
> > + reg = <0x0 0x20331000 0x0 0xc>;
> > + #address-cells = <0x2>;
> > + #size-cells = <0x2>;
> > + ranges;
> > +
> > + counter@...300e8 {
> > + compatible = "intel,keembay-counter";
> > + reg = <0x0 0x203300e8 0x0 0x8>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
>
> Don't show status in examples.
OK, I'll remove it.
Thanks!
Shruthi
>
> > + };
> > +
> > + timer@...30010 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330010 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30020 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330020 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30030 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330030 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30040 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330040 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30050 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330050 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30060 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330060 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30070 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330070 0x0 0xc>;
> > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > +
> > + timer@...30080 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x0 0x20330080 0x0 0xc>;
> > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + status = "okay";
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.17.1
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