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Message-ID: <f3d84841a80e4244887939624f6d3c10@AcuMS.aculab.com>
Date: Fri, 4 Jun 2021 09:02:29 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Palmer Dabbelt' <palmer@...belt.com>,
Anup Patel <Anup.Patel@....com>
CC: "guoren@...nel.org" <guoren@...nel.org>,
"anup@...infault.org" <anup@...infault.org>,
"drew@...gleboard.org" <drew@...gleboard.org>,
Christoph Hellwig <hch@....de>,
"wefu@...hat.com" <wefu@...hat.com>,
"lazyparser@...il.com" <lazyparser@...il.com>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"linux-sunxi@...ts.linux.dev" <linux-sunxi@...ts.linux.dev>,
"guoren@...ux.alibaba.com" <guoren@...ux.alibaba.com>,
Paul Walmsley <paul.walmsley@...ive.com>
Subject: RE: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support
From: Palmer Dabbelt
> Sent: 03 June 2021 16:39
...
> An example here would be the errata: every system has errata of some
> sort, so if we start flipping off various vendor's errata Kconfigs
> you'll end up with kernels that only function properly on some systems.
> That's fine with me, as long as it's possible to turn on all vendor's
> errata Kconfigs at the same time and the resulting kernel functions
> correctly on all systems.
ISTM that if you can (easily) detect the errata then the detection
should be left it - but the kernel fail to boot if the system
needs the errata fixed.
The same would be needed for DMA in systems with non-coherent memory.
Only a hardware engineer would build a system with non-coherent memory
and without the ability to do uncached accesses and flush/invalidate
small sections of cache.
Mind you we did get a dual-cpu system that didn't have cache-coherency
between the cpus! That was singularly useless.
David
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