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Date: Sun, 6 Jun 2021 09:04:07 +0000
From: guoren@...nel.org
To: guoren@...nel.org, anup.patel@....com, palmerdabbelt@...gle.com,
arnd@...db.de, wens@...e.org, maxime@...no.tech,
drew@...gleboard.org, liush@...winnertech.com,
lazyparser@...il.com, wefu@...hat.com
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arch@...r.kernel.org, linux-sunxi@...ts.linux.dev,
Guo Ren <guoren@...ux.alibaba.com>,
Atish Patra <atish.patra@....com>,
Christoph Hellwig <hch@....de>
Subject: [RFC PATCH v2 09/11] riscv: soc: Initial DTS for Allwinner D1 NeZha board
From: Guo Ren <guoren@...ux.alibaba.com>
Add initial DTS for Allwinner D1 NeZha board having only essential
devices (uart, dummy, clock, reset, clint, plic, etc).
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Co-Developed-by: Liu Shaohua <liush@...winnertech.com>
Signed-off-by: Liu Shaohua <liush@...winnertech.com>
Cc: Anup Patel <anup.patel@....com>
Cc: Atish Patra <atish.patra@....com>
Cc: Christoph Hellwig <hch@....de>
Cc: Chen-Yu Tsai <wens@...e.org>
Cc: Drew Fustini <drew@...gleboard.org>
Cc: Maxime Ripard <maxime@...no.tech>
Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
Cc: Wei Fu <wefu@...hat.com>
Cc: Wei Wu <lazyparser@...il.com>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/allwinner/Makefile | 2 +
.../boot/dts/allwinner/allwinner-d1-nezha-kit.dts | 29 ++++++++
arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi | 84 ++++++++++++++++++++++
4 files changed, 116 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index fe996b8..3e7b264 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -2,5 +2,6 @@
subdir-y += sifive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += allwinner
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
new file mode 100644
index 00000000..4adbf4b
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb
diff --git a/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
new file mode 100644
index 00000000..cd9f7c9
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Allwinner D1 NeZha Kit";
+ compatible = "allwinner,d1-nezha-kit";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = &serial0;
+ };
+
+ memory@...00000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+
+ soc {
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
new file mode 100644
index 00000000..11cd938
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Allwinner D1 Soc";
+ compatible = "allwinner,d1-nezha-kit";
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <2400000>;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcv";
+ mmu-type = "riscv,sv39";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ reset: reset-sample {
+ compatible = "thead,reset-sample";
+ plic-delegate = <0x0 0x101ffffc>;
+ };
+
+ clint: clint@...00000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <
+ &cpu0_intc 3 &cpu0_intc 7
+ >;
+ reg = <0x0 0x14000000 0x0 0x04000000>;
+ clint,has-no-64bit-mmio;
+ };
+
+ plic: interrupt-controller@...00000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ >;
+ reg = <0x0 0x10000000 0x0 0x04000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <200>;
+ };
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ };
+
+ serial0: serial@...0000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x02500000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <18>;
+ clocks = <&dummy_apb>;
+ status = "disabled";
+ };
+ };
+};
--
2.7.4
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