linux-kernel - [RFC] Adding A64FX hardware prefetch sysfs interface

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Message-ID: <OSBPR01MB2037D114B11153F00F233F8780389@OSBPR01MB2037.jpnprd01.prod.outlook.com>
Date:   Mon, 7 Jun 2021 01:39:21 +0000
From:   "tarumizu.kohei@...itsu.com" <tarumizu.kohei@...itsu.com>
To:     "'hpa@...or.com'" <hpa@...or.com>,
        "'tglx@...utronix.de'" <tglx@...utronix.de>,
        "'mingo@...hat.com'" <mingo@...hat.com>,
        "'x86@...nel.org'" <x86@...nel.org>,
        "'linux-kernel@...r.kernel.org'" <linux-kernel@...r.kernel.org>
CC:     "tarumizu.kohei@...itsu.com" <tarumizu.kohei@...itsu.com>
Subject: [RFC] Adding A64FX hardware prefetch sysfs interface

Hello

I'm Kohei Tarumizu from Fujitsu Limited. 

Fujitsu A64FX processor implements a vendor specific function, the HPC extensions[1].
A64FX has some registers for HPC extensions.
We would like to use the register IMP_PF_STREAM_DETECT_CTRL_EL0 for tuning the hardware prefetch, but it's not accessible from userspace.
We are considering to implement a kernel common interface via sysfs as a way to control IMP_PF_STREAM_DETECT_CTRL_EL0 from userspace.
FYI, A64FX also has registers (e.g. IMP_PF_INJECTION_*) to control the behavior of the hardware prefetch from the software using "HPC tag address override", but this time we don't considered.

[1]https://github.com/fujitsu/A64FX/tree/master/doc/
   A64FX_Specification_HPC_Extension_v1_EN.pdf

This register is similar to the MSR registers 0x1A4(MSR_MISC_FEATURE_CONTROL)[2] and its details are described in [Similarity of each register].
>From the discussion about the MSR driver, I understood it is not good idea to access registers directly from userspace, and that we want to move it to the proper interface.
We think it would be better to have the common interface which can control these registers in the future.
Therefore, we would like to design new sysfs interface, could you give me some advice?

[2]https://software.intel.com/content/www/us/en/develop/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors.html

[Similarity of each register]
* Settings for Hardware Prefetch
  These registers enable or disable hardware prefetching for L1/L2 cache.
  The A64FX's register also have "Prefetch Distance (bit: [27:24], [19:16])" and "Reliableness attribute for prefetch access (bit: [55], [54])".
* Not accessible from userspace
  In the expected usage scene (e.g. User wants to disable hardware prefetch), it is necessary to be able to access from the userspace.
* Share settings on a per-CPU basis
  A64FX's register is used in HPC applications and assumes that the process is bound to one core.

Currently, the path name has not been decided yet, but we consider of the following structure like cpufreq(/sys/devices/system/cpu/[CPUNUM]/cpufreq).

/sys/devices/system/cpu/[CPUNUM]/prefetcher/
    l1_enable   : This sets or displays whether hardware prefetch is enabled for L1 cache.
    l2_enable   : This sets or displays whether hardware prefetch is enabled for L2 cache.
    l1_dist     : This sets or displays whether hardware prefetch distance for L1 cache.
    l2_dist     : This sets or displays whether hardware prefetch distance for L2 cache.
    l1_reliable : This sets or displays whether reliableness attribute for prefetch access for L1 cache.
    l2_reliable : This sets or displays whether reliableness attribute for prefetch access for L2 cache.

We would like to implement only the enablement interface, if the A64FX-specific parameters ("dist" and "reliable") are not accepted.

Best regerds
Kohei Tarumizu