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Message-Id: <20210609140412.16058-5-jon.lin@rock-chips.com>
Date: Wed, 9 Jun 2021 22:04:07 +0800
From: Jon Lin <jon.lin@...k-chips.com>
To: linux-spi@...r.kernel.org
Cc: jon.lin@...k-chips.com, broonie@...nel.org, robh+dt@...nel.org,
heiko@...ech.de, jbx6244@...il.com, hjc@...k-chips.com,
yifeng.zhao@...k-chips.com, sugar.zhang@...k-chips.com,
linux-rockchip@...ts.infradead.org, linux-mtd@...ts.infradead.org,
p.yadav@...com, macroalpha82@...il.com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
mturquette@...libre.com, sboyd@...nel.org,
linux-clk@...r.kernel.org, Elaine Zhang <zhangqing@...k-chips.com>
Subject: [PATCH v7 4/9] clk: rockchip: rk3036: fix up the sclk_sfc parent error
Choose the correct pll
Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
Signed-off-by: Jon Lin <jon.lin@...k-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None
drivers/clk/rockchip/clk-rk3036.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 91d56ad45817..1986856d94b2 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
+PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 4, GFLAGS),
- COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
--
2.17.1
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