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Message-ID: <MWHPR11MB18864D52718BD84E32F7E1B78C369@MWHPR11MB1886.namprd11.prod.outlook.com>
Date: Wed, 9 Jun 2021 02:52:53 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: David Gibson <david@...son.dropbear.id.au>
CC: Jean-Philippe Brucker <jean-philippe@...aro.org>,
"Jiang, Dave" <dave.jiang@...el.com>,
"Raj, Ashok" <ashok.raj@...el.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
Jonathan Corbet <corbet@....net>,
David Woodhouse <dwmw2@...radead.org>,
Jason Wang <jasowang@...hat.com>,
LKML <linux-kernel@...r.kernel.org>,
Kirti Wankhede <kwankhede@...dia.com>,
"Alex Williamson (alex.williamson@...hat.com)"
<alex.williamson@...hat.com>,
"iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
Jason Gunthorpe <jgg@...dia.com>,
"Robin Murphy" <robin.murphy@....com>
Subject: RE: [RFC] /dev/ioasid uAPI proposal
> From: David Gibson <david@...son.dropbear.id.au>
> Sent: Tuesday, June 8, 2021 8:50 AM
>
> On Thu, Jun 03, 2021 at 06:49:20AM +0000, Tian, Kevin wrote:
> > > From: David Gibson
> > > Sent: Thursday, June 3, 2021 1:09 PM
> > [...]
> > > > > In this way the SW mode is the same as a HW mode with an infinite
> > > > > cache.
> > > > >
> > > > > The collaposed shadow page table is really just a cache.
> > > > >
> > > >
> > > > OK. One additional thing is that we may need a 'caching_mode"
> > > > thing reported by /dev/ioasid, indicating whether invalidation is
> > > > required when changing non-present to present. For hardware
> > > > nesting it's not reported as the hardware IOMMU will walk the
> > > > guest page table in cases of iotlb miss. For software nesting
> > > > caching_mode is reported so the user must issue invalidation
> > > > upon any change in guest page table so the kernel can update
> > > > the shadow page table timely.
> > >
> > > For the fist cut, I'd have the API assume that invalidates are
> > > *always* required. Some bypass to avoid them in cases where they're
> > > not needed can be an additional extension.
> > >
> >
> > Isn't a typical TLB semantics is that non-present entries are not
> > cached thus invalidation is not required when making non-present
> > to present?
>
> Usually, but not necessarily.
>
> > It's true to both CPU TLB and IOMMU TLB.
>
> I don't think it's entirely true of the CPU TLB on all ppc MMU models
> (of which there are far too many).
>
> > In reality
> > I feel there are more usages built on hardware nesting than software
> > nesting thus making default following hardware TLB behavior makes
> > more sense...
>
> I'm arguing for always-require-invalidate because it's strictly more
> general. Requiring the invalidate will support models that don't
> require it in all cases; we just make the invalidate a no-op. The
> reverse is not true, so we should tackle the general case first, then
> optimize.
>
It makes sense. Will adopt this way.
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