Message-ID: <20210609140521.3038e40e@xhacker.debian>
Date:   Wed, 9 Jun 2021 14:05:21 +0800
From:   Jisheng Zhang <Jisheng.Zhang@...aptics.com>
To:     Guo Ren <guoren@...nel.org>
Cc:     Nick Kossifidis <mick@....forth.gr>,
        Christoph Hellwig <hch@....de>,
        Drew Fustini <drew@...gleboard.org>,
        Anup Patel <anup.patel@....com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>, wefu@...hat.com,
        "Wei Wu ( 吴伟)" <lazyparser@...il.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        linux-sunxi@...ts.linux.dev, Guo Ren <guoren@...ux.alibaba.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Benjamin Koch <snowball@...b.de>,
        Matteo Croce <mcroce@...ux.microsoft.com>,
        Wei Fu <tekkamanninja@...il.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support

On Wed, 9 Jun 2021 11:28:19 +0800
Guo Ren <guoren@...nel.org> wrote:


> 
> 
> On Mon, Jun 7, 2021 at 2:14 AM Nick Kossifidis <mick@....forth.gr> wrote:
> >
> > Στις 2021-05-20 04:45, Guo Ren έγραψε:  
> > > On Wed, May 19, 2021 at 2:53 PM Christoph Hellwig <hch@....de> wrote:  
> > >>
> > >> On Tue, May 18, 2021 at 11:44:35PM -0700, Drew Fustini wrote:  
> > >> > This patch series looks like it might be useful for the StarFive JH7100
> > >> > [1] [2] too as it has peripherals on a non-coherent interconnect. GMAC,
> > >> > USB and SDIO require that the L2 cache must be manually flushed after
> > >> > DMA operations if the data is intended to be shared with U74 cores [2].  
> > >>
> > >> Not too much, given that the SiFive lineage CPUs have an uncached
> > >> window, that is a totally different way to allocate uncached memory.  
> > > It's a very big MIPS smell. What's the attribute of the uncached
> > > window? (uncached + strong-order/ uncached + weak, most vendors still
> > > use AXI interconnect, how to deal with a bufferable attribute?) In
> > > fact, customers' drivers use different ways to deal with DMA memory in
> > > non-coherent SOC. Most riscv SOC vendors are from ARM, so giving them
> > > the same way in DMA memory is a smart choice. So using PTE attributes
> > > is more suitable.
> > >

<snip>

> > > 4.4.1
> > > The draft supports custom attribute bits in PTE.
> > >  
> >
> > Not only it doesn't support custom attributes on PTEs:
> >
> > "Bits63–54 are reserved for future standard use and must be zeroed by
> > software for forward compatibility."
> >
> > It also goes further to say that:
> >
> > "if any of these bits are set, a page-fault exception is raised"  
> Agree, when our processor's mmu works in compatible mmu, we must keep
> "Bits63–54 bit" zero in Linux.
> So, I think this is the first version of the PTE format.
> 
> If the "PBMT" extension proposal is approved, it will cause the second
> version of the PTE format.
> 
> Maybe in the future, we'll get more versions of the PTE formats.
> 
> So, seems Linux must support multi versions of PTE formats with one
> Image, right?
> 
> Okay, we could stop arguing with the D1 PTE format. And talk about how
> to let Linux support multi versions of PTE formats that come from the
> future RISC-V privilege spec.
> 

Just my humble opinion:
When those bits(63~54) usage are standardized in future RISC-V privilege spec
generic Image can still be supported with the following solutions:

*alternative patch only fly:
If the bit is only need to be set during init, we may insert nop instruction(s)
at proper place, then patch the nop into set_the_target_bit instruction(s) by
hart's feature.

*normal check feature then use:
If the feature needs a bit complex code, we could go through the "feature check
then use". static key tech can be used here to avoid branches.

Powered by blists - more mailing lists