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Date: Wed, 09 Jun 2021 13:51:39 +0300 From: Artem Bityutskiy <artem.bityutskiy@...ux.intel.com> To: Chen Yu <yu.c.chen@...el.com>, linux-pm@...r.kernel.org Cc: "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>, Len Brown <len.brown@...el.com>, Zhang Rui <rui.zhang@...el.com>, linux-kernel@...r.kernel.org Subject: Re: [PATCH][v2] intel_idle: Adjust the SKX C6 latency and residency if PC6 is disabled On Fri, 2021-05-28 at 11:20 +0800, Chen Yu wrote: > Currently cpuidle assumes worst-case C-state parameters, and so C6 > is described with PC6 parameters, which is worst case for requesting > CC6. When PC6 is enabled, this is appropriate. But if PC6 is disabled > in BIOS, the exit latency and target_residency should be adjusted > accordingly. > > Exit latency: > Previously the C6 exit latency was measured when woken up from CC6/PC6. > With PC6 disabled, the C6 exit latency should be CC6/PC0. > > Target residency: > With PC6 disabled, idle duration within [CC6, PC6) would make the > idle governor choose C1E over C6. This would cause low energy-efficiency. > We should lower the bar to request C6 when PC6 is disabled. > > To fill this gap, check if PC6 is disabled in the BIOS in the > MSR_PKG_CST_CONFIG_CONTROL(0xe2). If so, use CC6/PC0 parameters as the > new exit latency. Meanwhile, update target_residency to 3 times of the new > exit latency. This is consistent with how intel_idle driver uses _CST to > calculate the target_residency. The consequence is that, the OS would > be more offen to choose C6 over C1E when PC6 is disabled. This is reasonable > because if the user is using C6, it implies that the user cares about energy, > so choosing C6 more frequently is in accordance with user requirement. > > The new exit latency of CC6/PC0 92us was from wult[1] result on SKX, which was > measured via NIC wakeup from 99.99th latency. Besides SKX, the CLX and CPX > both have the same CPU model number. And since they have similar CC6 exit latency > to SKX, 96us and 89us respectively, reuse the value of SKX. > > There is concern that if we should introduce a more generic solution > rather than optimizing on each platforms. However consider the > code complexity and different PC6 bit interpretation on different > platforms, tune the code per platform seems to be an acceptable trade-off. > > [1] https://intel.github.io/wult/ > > Suggested-by: Len Brown <len.brown@...el.com> > Signed-off-by: Chen Yu <yu.c.chen@...el.com> > --- > v2: Simplify the commit log to not mention C3/PC3. (Artem) > Confirm the exit latency on CLX and CPX.(Artem) Reviewed-by: Artem Bityutskiy <artem.bityutskiy@...ux.intel.com>
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