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Message-ID: <20210609154154.54aa5f06@xps13>
Date: Wed, 9 Jun 2021 15:41:54 +0200
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc: Naga Sureshkumar Relli <nagasure@...inx.com>,
Michal Simek <monstr@...str.eu>,
Amit Kumar Mahapatra <akumarma@...inx.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Rob Herring <robh+dt@...nel.org>,
linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org,
Vignesh Raghavendra <vigneshr@...com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
helmut.grohne@...enta.de, Srinivas Goud <sgoud@...inx.com>,
Siva Durga Prasad Paladugu <sivadur@...inx.com>,
Richard Weinberger <richard@....at>,
Tudor Ambarus <Tudor.Ambarus@...rochip.com>
Subject: Re: [PATCH v22 15/18] MAINTAINERS: Add PL353 SMC entry
Hi Krzysztof,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com> wrote on Wed, 9
Jun 2021 15:23:11 +0200:
> On 09/06/2021 10:01, Miquel Raynal wrote:
> > Add Naga from Xilinx and myself responsible of this driver.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
> > ---
> > MAINTAINERS | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
>
> Memory controller bits look good to me, except few things in bindings. I
> can take them up to this patch, for which I would need also Ack from
> Naga Sureshkumar Relli confirming he will co-maintain this code.
Sure. I would also expect Rob to Ack the yaml conversion possibly.
I am waiting for your feedback on a couple of questions and then I will
respin the series.
> I assume the NAND driver depends on this, so I can prepare a stable tag
> with the memory controller part, if needed.
Absolutely, that would be great.
Thanks,
Miquèl
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