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Message-ID: <87r1h9kdmx.fsf@stealth>
Date: Thu, 10 Jun 2021 23:17:26 +0900
From: Punit Agrawal <punitagrawal@...il.com>
To: Marc Zyngier <maz@...nel.org>
Cc: helgaas@...nel.org, robh+dt@...nel.org,
linux-rockchip@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, alexandru.elisei@....com, wqu@...e.com,
robin.murphy@....com, pgwipeout@...il.com, ardb@...nel.org,
briannorris@...omium.org, shawn.lin@...k-chips.com
Subject: Re: [PATCH v3 0/4] PCI: of: Improvements to handle 64-bit attribute
for non-prefetchable ranges
Hi Marc,
Marc Zyngier <maz@...nel.org> writes:
> Hi Punit,
>
> On Mon, 07 Jun 2021 12:28:52 +0100,
> Punit Agrawal <punitagrawal@...il.com> wrote:
>>
>> Hi,
>>
>> This is the third iteration to improve handling of the 64-bit
>> attribute on non-prefetchable host bridge ranges. Previous version can
>> be found at [0][1].
>>
>> This version is a small update over the previous version - changelog
>> below. If there is no futher feedback on the patches, please consider
>> merging them.
>
> Thanks for this. This brings my test machine back to life:
>
> Acked-by: Marc Zyngier <maz@...nel.org>
> Tested-by: Marc Zyngier <maz@...nel.org>
Thanks for taking the patches for a spin. Based on the comments on Patch
1, there'll at least be another update. I'll copy you when I send that
out.
Thanks,
Punit
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