linux-kernel - Re: [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance

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Date:   Thu, 10 Jun 2021 12:36:57 -0500
From:   Chris Morgan <macroalpha82@...il.com>
To:     Jon Lin <jon.lin@...k-chips.com>
Cc:     linux-spi@...r.kernel.org, broonie@...nel.org, robh+dt@...nel.org,
        heiko@...ech.de, jbx6244@...il.com, hjc@...k-chips.com,
        yifeng.zhao@...k-chips.com, sugar.zhang@...k-chips.com,
        linux-rockchip@...ts.infradead.org, linux-mtd@...ts.infradead.org,
        p.yadav@...com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        mturquette@...libre.com, sboyd@...nel.org,
        linux-clk@...r.kernel.org, Chris Morgan <macromorgan@...mail.com>
Subject: Re: [PATCH v7 9/9] arm64: dts: rockchip: Enable SFC for Odroid Go
 Advance

On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@...mail.com>
> 
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@...mail.com>
> Signed-off-by: Jon Lin <jon.lin@...k-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
> 
>  .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;

Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX.  When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)

The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.

Thank you.

> +	};
> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
>