linux-kernel - Re: [PATCH 1/4] x86/msr: Define new bits in TSX_FORCE

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Message-ID: <20210611213129.py2jyfzy37czegkm@gupta-dev2.localdomain>
Date:   Fri, 11 Jun 2021 14:31:29 -0700
From:   Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Jonathan Corbet <corbet@....net>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>, x86@...nel.org,
        "H. Peter Anvin" <hpa@...or.com>,
        "Paul E. McKenney" <paulmck@...nel.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        Andrew Morton <akpm@...ux-foundation.org>,
        "Maciej W. Rozycki" <macro@...am.me.uk>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Vlastimil Babka <vbabka@...e.cz>,
        Tony Luck <tony.luck@...el.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Sean Christopherson <seanjc@...gle.com>,
        Kyung Min Park <kyung.min.park@...el.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
        Tom Lendacky <thomas.lendacky@....com>,
        Juergen Gross <jgross@...e.com>,
        Krish Sadhukhan <krish.sadhukhan@...cle.com>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Joerg Roedel <jroedel@...e.de>,
        Victor Ding <victording@...gle.com>,
        Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
        Brijesh Singh <brijesh.singh@....com>,
        Dave Hansen <dave.hansen@...el.com>,
        Mike Rapoport <rppt@...nel.org>,
        Anthony Steinhauser <asteinhauser@...gle.com>,
        Anand K Mistry <amistry@...gle.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Miguel Ojeda <ojeda@...nel.org>, Joe Perches <joe@...ches.com>,
        linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org
Subject: Re: [PATCH 1/4] x86/msr: Define new bits in TSX_FORCE_ABORT MSR

On 11.06.2021 10:39, Borislav Petkov wrote:
>On Wed, Jun 09, 2021 at 01:58:02PM -0700, Pawan Gupta wrote:
>> Intel client processors that support IA32_TSX_FORCE_ABORT MSR related to
>> perf counter interaction [1] received a microcode update that deprecates
>> Transactional Synchronization Extension (TSX) feature. MSR
>> IA32_TSX_FORCE_ABORT bit FORCE_ABORT_RTM now defaults to 1, writes to
>> this bit are ignored. A new bit TSX_CPUID_CLEAR clears the TSX related
>> CPUID bits.
>>
>> Below is the summary of changes to IA32_TSX_FORCE_ABORT MSR:
>>
>>   Bit 0: FORCE_ABORT_RTM (legacy bit, new default=1) Status bit that
>>   indicates if RTM transactions are always aborted. This bit is
>>   essentially !SDV_ENABLE_RTM(Bit 2). Writes to this bit are ignored.
>>
>>   Bit 1: TSX_CPUID_CLEAR (new bit, default=0) When set, CPUID.HLE = 0
>>   and CPUID.RTM = 0.
>>
>>   Bit 2: SDV_ENABLE_RTM (new bit, default=0) When clear, XBEGIN will
>>   always abort with EAX code 0. When set, XBEGIN will not be forced to
>>   abort (but will always abort in SGX enclaves). This bit is intended to
>>   be SDV-only. If this bit is set transactional atomicity correctness is
>
>SDV?

Sorry should have expanded this. It stands for Software Development
Vehicle (SDV), i.e. developer systems.

>>   not certain.
>>
>> Performance monitoring counter 3 is usable in all cases, regardless of
>> the value of above bits.
>>
>> A new CPUID bit CPUID.RTM_ALWAYS_ABORT (CPUID 7.EDX[11]) is added to
>> indicate the status of always abort behavior.
>>
>> Define these new CPUID and MSR bits.
>>
>> [1] Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory
>>     http://cdrdv2.intel.com/v1/dl/getContent/604224
>
>That link does not look stable enough to put in commit messages.
>Besides, you've said it all in the commit message already.

The important part is the Document ID 604224. I can remove the link
completely, or add the document ID to it, whatever you suggest:

	[1] Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory
	    http://cdrdv2.intel.com/v1/dl/getContent/604224 (Document ID 604224).
							     ^^^^^^^^^^^^^^^^^^

Thanks,
Pawan