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Date: Thu, 10 Jun 2021 22:49:48 -0500
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Konrad Dybcio <konrad.dybcio@...ainline.org>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, martin.botka@...ainline.org,
angelogioacchino.delregno@...ainline.org,
marijn.suijten@...ainline.org, jamipkettunen@...ainline.org,
Andy Gross <agross@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] pinctrl: qcom: Add MDM9607 pinctrl driver
On Wed 02 Jun 03:05 CDT 2021, Konrad Dybcio wrote:
> Add a pinctrl driver to allow for managing SoC pins.
>
This looks really good, just a few of small things below.
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-mdm9607.c | 1124 ++++++++++++++++++++++++
> 3 files changed, 1133 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-mdm9607.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 6853a896c476..34a7b9322b9b 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -88,6 +88,14 @@ config PINCTRL_MSM8960
> This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> Qualcomm TLMM block found in the Qualcomm 8960 platform.
>
> +config PINCTRL_MDM9607
> + tristate "Qualcomm 9607 pin controller driver"
> + depends on GPIOLIB && OF
> + depends on PINCTRL_MSM
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm TLMM block found in the Qualcomm 9607 platform.
> +
> config PINCTRL_MDM9615
> tristate "Qualcomm 9615 pin controller driver"
> depends on GPIOLIB && OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index d4301fbb7274..a60b075b3054 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
> obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
> obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
> +obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
> obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
> obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c
[..]
> +enum mdm9607_functions {
> + msm_mux_blsp_spi3,
The order of these doesn't matter, so please sort them alphabetically.
> + msm_mux_gpio,
> + msm_mux_blsp_uart3,
> + msm_mux_qdss_tracedata_a,
> + msm_mux_bimc_dte1,
> + msm_mux_blsp_i2c3,
> + msm_mux_qdss_traceclk_a,
> + msm_mux_bimc_dte0,
> + msm_mux_qdss_cti_trig_in_a1,
> + msm_mux_blsp_spi2,
> + msm_mux_blsp_uart2,
> + msm_mux_blsp_uim2,
> + msm_mux_blsp_i2c2,
> + msm_mux_qdss_tracectl_a,
> + msm_mux_sensor_int2,
> + msm_mux_blsp_spi5,
> + msm_mux_blsp_uart5,
> + msm_mux_ebi2_lcd,
> + msm_mux_m_voc,
> + msm_mux_sensor_int3,
> + msm_mux_sensor_en,
> + msm_mux_blsp_i2c5,
> + msm_mux_ebi2_a,
> + msm_mux_qdss_tracedata_b,
> + msm_mux_sensor_rst,
> + msm_mux_blsp2_spi,
> + msm_mux_blsp_spi1,
> + msm_mux_blsp_uart1,
> + msm_mux_blsp_uim1,
> + msm_mux_blsp3_spi,
> + msm_mux_gcc_gp2_clk_b,
> + msm_mux_gcc_gp3_clk_b,
> + msm_mux_blsp_i2c1,
> + msm_mux_gcc_gp1_clk_b,
> + msm_mux_blsp_spi4,
> + msm_mux_blsp_uart4,
> + msm_mux_rcm_marker1,
> + msm_mux_blsp_i2c4,
> + msm_mux_qdss_cti_trig_out_a1,
> + msm_mux_rcm_marker2,
> + msm_mux_qdss_cti_trig_out_a0,
> + msm_mux_blsp_spi6,
> + msm_mux_blsp_uart6,
> + msm_mux_pri_mi2s_ws_a,
> + msm_mux_ebi2_lcd_te_b,
> + msm_mux_blsp1_spi,
> + msm_mux_backlight_en_b,
> + msm_mux_pri_mi2s_data0_a,
> + msm_mux_pri_mi2s_data1_a,
> + msm_mux_blsp_i2c6,
> + msm_mux_ebi2_a_d_8_b,
> + msm_mux_pri_mi2s_sck_a,
> + msm_mux_ebi2_lcd_cs_n_b,
> + msm_mux_touch_rst,
> + msm_mux_pri_mi2s_mclk_a,
> + msm_mux_pwr_nav_enabled_a,
> + msm_mux_ts_int,
> + msm_mux_sd_write,
> + msm_mux_pwr_crypto_enabled_a,
> + msm_mux_codec_rst,
> + msm_mux_adsp_ext,
> + msm_mux_atest_combodac_to_gpio_native,
> + msm_mux_uim2_data,
> + msm_mux_gmac_mdio,
> + msm_mux_gcc_gp1_clk_a,
> + msm_mux_uim2_clk,
> + msm_mux_gcc_gp2_clk_a,
> + msm_mux_eth_irq,
> + msm_mux_uim2_reset,
> + msm_mux_gcc_gp3_clk_a,
> + msm_mux_eth_rst,
> + msm_mux_uim2_present,
> + msm_mux_prng_rosc,
> + msm_mux_uim1_data,
> + msm_mux_uim1_clk,
> + msm_mux_uim1_reset,
> + msm_mux_uim1_present,
> + msm_mux_gcc_plltest,
> + msm_mux_uim_batt,
> + msm_mux_coex_uart,
> + msm_mux_codec_int,
> + msm_mux_qdss_cti_trig_in_a0,
> + msm_mux_atest_bbrx1,
> + msm_mux_cri_trng0,
> + msm_mux_atest_bbrx0,
> + msm_mux_cri_trng,
> + msm_mux_qdss_cti_trig_in_b0,
> + msm_mux_atest_gpsadc_dtest0_native,
> + msm_mux_qdss_cti_trig_out_b0,
> + msm_mux_qdss_tracectl_b,
> + msm_mux_qdss_traceclk_b,
> + msm_mux_pa_indicator,
> + msm_mux_modem_tsync,
> + msm_mux_nav_tsync_out_a,
> + msm_mux_nav_ptp_pps_in_a,
> + msm_mux_ptp_pps_out_a,
> + msm_mux_gsm0_tx,
> + msm_mux_qdss_cti_trig_in_b1,
> + msm_mux_cri_trng1,
> + msm_mux_qdss_cti_trig_out_b1,
> + msm_mux_ssbi1,
> + msm_mux_atest_gpsadc_dtest1_native,
> + msm_mux_ssbi2,
> + msm_mux_atest_char3,
> + msm_mux_atest_char2,
> + msm_mux_atest_char1,
> + msm_mux_atest_char0,
> + msm_mux_atest_char,
> + msm_mux_ebi0_wrcdc,
> + msm_mux_ldo_update,
> + msm_mux_gcc_tlmm,
> + msm_mux_ldo_en,
> + msm_mux_dbg_out,
> + msm_mux_atest_tsens,
> + msm_mux_lcd_rst,
> + msm_mux_wlan_en1,
> + msm_mux_nav_tsync_out_b,
> + msm_mux_nav_ptp_pps_in_b,
> + msm_mux_ptp_pps_out_b,
> + msm_mux_pbs0,
> + msm_mux_sec_mi2s,
> + msm_mux_pwr_modem_enabled_a,
> + msm_mux_pbs1,
> + msm_mux_pwr_modem_enabled_b,
> + msm_mux_pbs2,
> + msm_mux_pwr_nav_enabled_b,
> + msm_mux_pwr_crypto_enabled_b,
> + msm_mux_NA,
> +};
[..]
> +static const struct msm_pingroup mdm9607_groups[] = {
> + PINGROUP(0, blsp_uart3, blsp_spi3, NA, NA, NA, NA, NA,
> + qdss_tracedata_a, NA),
After doing a few platforms I realized that replacing NA with _ makes
this easier to read.
And please avoid breaking these lines.
> + PINGROUP(1, blsp_uart3, blsp_spi3, NA, NA, NA, NA, NA,
> + qdss_tracedata_a, bimc_dte1),
[..]
> + PINGROUP(79, sec_mi2s, NA, pwr_crypto_enabled_b, NA, qdss_tracedata_a,
> + NA, NA, NA, NA),
> + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6),
> + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3),
> + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0),
> + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6),
> + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3),
> + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0),
> + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0),
> + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5),
> + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10),
> + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15),
> + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20),
> + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25),
> +};
> +
> +#define NUM_GPIO_PINGROUPS 92
Only 80 of these makes sense to poke through the gpio framework, so this
should be 80...
> +
> +static const struct msm_pinctrl_soc_data mdm9607_pinctrl = {
> + .pins = mdm9607_pins,
> + .npins = ARRAY_SIZE(mdm9607_pins),
> + .functions = mdm9607_functions,
> + .nfunctions = ARRAY_SIZE(mdm9607_functions),
> + .groups = mdm9607_groups,
> + .ngroups = ARRAY_SIZE(mdm9607_groups),
> + .ngpios = NUM_GPIO_PINGROUPS,
> +};
> +
> +static int mdm9607_pinctrl_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &mdm9607_pinctrl);
> +}
> +
> +static const struct of_device_id mdm9607_pinctrl_of_match[] = {
> + { .compatible = "qcom,mdm9607-pinctrl", },
qcom,mdm9607-tlmm
> + { },
No need to this comma.
Thanks,
Bjorn
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