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Message-ID: <20210611055606.GB6950@thinkpad>
Date: Fri, 11 Jun 2021 11:26:06 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Andreas Färber <afaerber@...e.de>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-actions@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] ARM: dts: owl-s500-roseapplepi: Add ethernet support
On Fri, Jun 11, 2021 at 12:09:22AM +0300, Cristian Ciocaltea wrote:
> Add pinctrl configuration for enabling the Ethernet MAC on RoseapplePi
> SBC. Additionally, provide the necessary properties for the generic S500
> ethernet node in order to setup PHY and MDIO.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...il.com>
> ---
> arch/arm/boot/dts/owl-s500-roseapplepi.dts | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> index b8c5db2344aa..bffabc7eaa50 100644
> --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
> @@ -225,6 +225,38 @@ bias1-pinconf {
> bias-pull-down;
> };
> };
> +
> + ethernet_pins: ethernet-pins {
> + txd01-pinmux {
> + groups = "rmii_txd0_mfp", "rmii_txd1_mfp";
> + function = "eth_rmii";
> + };
> +
> + rxd01-pinmux {
> + groups = "rmii_rxd0_mfp", "rmii_rxd1_mfp";
> + function = "eth_rmii";
> + };
> +
> + txen_rxer-pinmux {
> + groups = "rmii_txen_mfp", "rmii_rxen_mfp";
> + function = "eth_rmii";
> + };
> +
> + crs_dv_ref_clk-pinmux {
> + groups = "rmii_crs_dv_mfp", "rmii_ref_clk_mfp";
> + function = "eth_rmii";
Since the function is same, just club all the groups together.
> + };
> +
> + ref_clk-pinconf {
> + groups = "rmii_ref_clk_drv";
> + drive-strength = <2>;
> + };
> +
> + phy_clk-pinmux {
> + groups = "clko_25m_mfp";
> + function = "clko_25m";
> + };
Move this above node pinconf.
> + };
> };
>
> /* uSD */
> @@ -241,6 +273,30 @@ &mmc0 {
> vqmmc-supply = <&sd_vcc>;
> };
>
> +ðernet {
> + pinctrl-names = "default";
> + pinctrl-0 = <ðernet_pins>;
> + phy-mode = "rmii";
> + phy-handle = <ð_phy>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reset-gpios = <&pinctrl 88 GPIO_ACTIVE_LOW>; /* GPIOC24 */
> + reset-delay-us = <10000>;
> + reset-post-delay-us = <150000>;
reset-* properties belong to "ethernet-phy" node. Also, while adding new nodes
please run the dtbs_check and try to address the warnings.
Thanks,
Mani
> +
> + eth_phy: ethernet-phy@3 {
> + reg = <0x3>;
> + max-speed = <100>;
> + interrupt-parent = <&sirq>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> + };
> +};
> +
> &twd_timer {
> status = "okay";
> };
> --
> 2.32.0
>
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