Date:   Sun, 13 Jun 2021 08:14:54 +0200
From:   Alex Ghiti <alex@...ti.fr>
To:     Jisheng Zhang <jszhang3@...l.ustc.edu.cn>,
        Palmer Dabbelt <palmer@...belt.com>
Cc:     emil.renner.berthing@...il.com,
        Paul Walmsley <paul.walmsley@...ive.com>,
        aou@...s.berkeley.edu, jszhang@...nel.org,
        Christoph Hellwig <hch@...radead.org>, zong.li@...ive.com,
        anup@...infault.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/4] riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED

Hi,

Le 13/06/2021 à 02:44, Jisheng Zhang a écrit :
> On Sat, 12 Jun 2021 17:23:51 -0700 (PDT)
> Palmer Dabbelt <palmer@...belt.com> wrote:
> 
>> On Sat, 12 Jun 2021 16:23:03 PDT (-0700), emil.renner.berthing@...il.com wrote:
>>> On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@...ti.fr> wrote:
>>>>
>>>> Make the physical RAM base address available for all kernels, not only
>>>> XIP kernels as it will allow to simplify address conversions macros.
>>>
>>> Am I just reading it wrong or won't this patch make it so that the same kernel
>>> can't run on two chips with physical ram starting at different addresses?
> 
> I mentioned this point in http://lists.infradead.org/pipermail/linux-riscv/2021-June/006840.html
> 
>>
>> IIUC we were in that position, at least without relocatable kernels.
>> Maybe I'm misunderstanding this, though?
> 
> Just my humble opinion, before this series patch, at least geneirc Image
> for RV64 + MMU + !XIP is doable.
> 

This patch declares that the physical ram address is at 0x8000_0000, 
whatever the chip, which may not be the case in practice. I did not 
expect Palmer would take this one and had planned to simply push a v5 
without the first 2 patches, but things happened this week that 
prevented me to do that. IMO, we should just wait for a v5 that I'll 
push when possible (probably today or in the coming days).

Thanks,

Alex

> Thanks
> 
>>
>>>
>>> /Emil
>>>   
>>>> ---
>>>>   arch/riscv/Kconfig | 6 ------
>>>>   1 file changed, 6 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>>> index b58596b141fc..3d8e7e4bb45c 100644
>>>> --- a/arch/riscv/Kconfig
>>>> +++ b/arch/riscv/Kconfig
>>>> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK
>>>>          def_bool y
>>>>          depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
>>>>
>>>> -config PHYS_RAM_BASE_FIXED
>>>> -       bool "Explicitly specified physical RAM address"
>>>> -       default n
>>>> -
>>>>   config PHYS_RAM_BASE
>>>>          hex "Platform Physical RAM address"
>>>> -       depends on PHYS_RAM_BASE_FIXED
>>>>          default "0x80000000"
>>>>          help
>>>>            This is the physical address of RAM in the system. It has to be
>>>> @@ -512,7 +507,6 @@ config XIP_KERNEL
>>>>          # This prevents XIP from being enabled by all{yes,mod}config, which
>>>>          # fail to build since XIP doesn't support large kernels.
>>>>          depends on !COMPILE_TEST
>>>> -       select PHYS_RAM_BASE_FIXED
>>>>          help
>>>>            Execute-In-Place allows the kernel to run from non-volatile storage
>>>>            directly addressable by the CPU, such as NOR flash. This saves RAM
>>>> --
>>>> 2.30.2
>>>>
>>>>
>>>> _______________________________________________
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>>>> linux-riscv@...ts.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>
>> _______________________________________________
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> 
> 
> 
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