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Message-ID: <87a6nsrdkm.wl-maz@kernel.org>
Date: Mon, 14 Jun 2021 10:38:17 +0100
From: Marc Zyngier <maz@...nel.org>
To: Anup Patel <anup@...infault.org>
Cc: Anup Patel <anup.patel@....com>,
Palmer Dabbelt <palmer@...belt.com>,
Palmer Dabbelt <palmerdabbelt@...gle.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Thomas Gleixner <tglx@...utronix.de>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Atish Patra <atish.patra@....com>,
Alistair Francis <Alistair.Francis@....com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>
Subject: Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver
On Sun, 13 Jun 2021 13:25:40 +0100,
Anup Patel <anup@...infault.org> wrote:
>
> On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@...nel.org> wrote:
> >
> > I'm sorry, but this really isn't an irqchip driver. This is a piece of
> > arch-specific code that uses *none* of the irq subsystem abstractions
> > apart from the IRQCHIP_DECLARE() macro.
>
> Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.
>
> Both ACLINT MSWI and SSWI are special devices providing only IPI
> support so I will re-think how to fit this.
It depends on how you think of IPIs in your architecture.
arm64 (and even now 32bit) have been moved to a mode where IPIs are
normal interrupts, as it helps with other things such as our pseudo
NMIs, and reduces code duplication. MIPS has done the same for a long
time (they don't have dedicated HW for that).
M.
--
Without deviation from the norm, progress is not possible.
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