| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 16 Jun 2021 01:32:14 +0800
From: Tinghan Shen <tinghan.shen@...iatek.com>
To: <robh+dt@...nel.org>, <matthias.bgg@...il.com>
CC: <devicetree@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>,
<seiya.wang@...iatek.com>, <wenst@...gle.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Kewei Xu <kewei.xu@...iatek.com>
Subject: [PATCH 08/27] arm64: dts: mt8195: add i2c dts
From: Kewei Xu <kewei.xu@...iatek.com>
add i2c dts config for mt8195 soc.
Signed-off-by: Kewei Xu <kewei.xu@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 105 +++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5463e7ba1061..9b002bb6d344 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -879,12 +879,117 @@
};
};
+ i2c5: i2c@...00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x10220580 0 0x80>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@...02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d02000 0 0x1000>,
+ <0 0x10220680 0 0x80>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
imp_iic_wrap_s: syscon@...03000 {
compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon";
reg = <0 0x11d03000 0 0x1000>;
#clock-cells = <1>;
};
+ i2c0: i2c@...00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e00000 0 0x1000>,
+ <0 0x10220080 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ i2c1: i2c@...01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e01000 0 0x1000>,
+ <0 0x10220200 0 0x80>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@...02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e02000 0 0x1000>,
+ <0 0x10220380 0 0x80>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@...03000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e03000 0 0x1000>,
+ <0 0x10220480 0 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@...04000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e04000 0 0x1000>,
+ <0 0x10220500 0 0x80>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
imp_iic_wrap_w: syscon@...05000 {
compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon";
reg = <0 0x11e05000 0 0x1000>;
--
2.18.0
Powered by blists - more mailing lists