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Message-ID: <20210615173233.26682-18-tinghan.shen@mediatek.com>
Date:   Wed, 16 Jun 2021 01:32:24 +0800
From:   Tinghan Shen <tinghan.shen@...iatek.com>
To:     <robh+dt@...nel.org>, <matthias.bgg@...il.com>
CC:     <devicetree@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>,
        <seiya.wang@...iatek.com>, <wenst@...gle.com>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Jason-JH Lin <jason-jh.lin@...iatek.com>
Subject: [PATCH 18/27] arm64: dts: mt8195: add dsc node

From: Jason-JH Lin <jason-jh.lin@...iatek.com>

add dsc node

Signed-off-by: Jason-JH Lin <jason-jh.lin@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 34f7e99d1fd2..0399aa8cf994 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1995,6 +1995,14 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 		};
 
+		dsc0: disp_dsc_wrap@...09000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@...1b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0

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