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Message-ID: <87bl86hl0h.ffs@nanos.tec.linutronix.de>
Date:   Tue, 15 Jun 2021 23:32:14 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Borislav Petkov <bp@...e.de>
Cc:     LKML <linux-kernel@...r.kernel.org>,
        Andy Lutomirski <luto@...nel.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Tony Luck <tony.luck@...el.com>,
        Yu-cheng Yu <yu-cheng.yu@...el.com>,
        Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Kan Liang <kan.liang@...ux.intel.com>
Subject: Re: [patch V2 08/52] x86/fpu: Sanitize xstateregs_set()

On Tue, Jun 15 2021 at 19:40, Borislav Petkov wrote:
> On Mon, Jun 14, 2021 at 05:44:16PM +0200, Thomas Gleixner wrote:
>> @@ -108,10 +110,10 @@ int xstateregs_set(struct task_struct *t
>>  		  const void *kbuf, const void __user *ubuf)
>>  {
>>  	struct fpu *fpu = &target->thread.fpu;
>> -	struct xregs_state *xsave;
>> +	struct xregs_state *tmpbuf = NULL;
>>  	int ret;
>>  
>> -	if (!boot_cpu_has(X86_FEATURE_XSAVE))
>> +	if (!static_cpu_has(X86_FEATURE_XSAVE))
>
> cpu_feature_enabled() - we're going to use only that thing from now on
> for simplicity.

Sure, I just run sed over the set.

>> +	fpu__prepare_write(fpu);
>
> Yikes, why isn't this function called
>
> fpu_invalidate_state(fpu)

Because...

>> +	/* mxcsr reserved bits must be masked to zero for historical reasons. */
>
> Wasn't that comment supposed to get some love?

See the next patch ...

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