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Message-ID: <CAAOTY_9M7bpvYM1bmZjkari=3f1uxAjOzs_UFhv10JTR0X4orw@mail.gmail.com>
Date: Wed, 16 Jun 2021 07:14:12 +0800
From: Chun-Kuang Hu <chunkuang.hu@...nel.org>
To: Tinghan Shen <tinghan.shen@...iatek.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
DTML <devicetree@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
Seiya Wang <seiya.wang@...iatek.com>, wenst@...gle.com,
Project_Global_Chrome_Upstream_Group@...iatek.com,
Jason-JH Lin <jason-jh.lin@...iatek.com>
Subject: Re: [PATCH 16/27] arm64: dts: mt8195: add display node
Hi, Tinghan:
Tinghan Shen <tinghan.shen@...iatek.com> 於 2021年6月16日 週三 上午5:37寫道：
>
> From: Jason-JH Lin <jason-jh.lin@...iatek.com>
>
> add display node.
>
> Signed-off-by: Jason-JH Lin <jason-jh.lin@...iatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 856b0e938009..f362288ad828 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1911,6 +1911,82 @@
> #clock-cells = <1>;
> };
>
> + vdosys_config@...1a000 {
> + compatible = "mediatek,mt8195-vdosys";
Where is the definition of this compatible?
> + reg = <0 0x1c01a000 0 0x1000>;
> + reg-names = "vdosys0_config";
> + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + };
> +
> + mutex: disp_mutex0@...16000 {
> + compatible = "mediatek,mt8195-disp-mutex";
Ditto.
> + reg = <0 0x1c016000 0 0x1000>;
> + reg-names = "vdo0_mutex";
> + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clock-names = "vdo0_mutex";
> + interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + ovl0: disp_ovl@...00000 {
> + compatible = "mediatek,mt8195-disp-ovl";
Ditto.
> + reg = <0 0x1c000000 0 0x1000>;
> + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> + };
> +
> + rdma0: disp_rdma@...02000 {
> + compatible = "mediatek,mt8195-disp-rdma";
Ditto.
> + reg = <0 0x1c002000 0 0x1000>;
> + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
> + };
> +
> + color0: disp_color@...03000 {
> + compatible = "mediatek,mt8195-disp-color";
Ditto.
> + reg = <0 0x1c003000 0 0x1000>;
> + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + };
> +
> + ccorr0: disp_ccorr@...04000 {
> + compatible = "mediatek,mt8195-disp-ccorr";
Ditto.
> + reg = <0 0x1c004000 0 0x1000>;
> + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + };
> +
> + aal0: disp_aal@...05000 {
> + compatible = "mediatek,mt8195-disp-aal";
Ditto.
> + reg = <0 0x1c005000 0 0x1000>;
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + };
> +
> + gamma0: disp_gamma@...06000 {
> + compatible = "mediatek,mt8195-disp-gamma";
Ditto.
> + reg = <0 0x1c006000 0 0x1000>;
> + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + };
> +
> + dither0: disp_dither@...07000 {
> + compatible = "mediatek,mt8195-disp-dither";
Ditto.
> + reg = <0 0x1c007000 0 0x1000>;
> + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + };
> +
> smi_common0: smi@...1b000 {
> compatible = "mediatek,mt8195-smi-common";
Ditto.
Regards,
Chun-Kuang.
> mediatek,common-id = <0>;
> --
> 2.18.0
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