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Message-ID: <CAAOTY__cE+wz3hjOobWNDNjie29NsDQiytP=mocbLJxuOF2+4Q@mail.gmail.com>
Date: Wed, 16 Jun 2021 07:30:19 +0800
From: Chun-Kuang Hu <chunkuang.hu@...nel.org>
To: Tinghan Shen <tinghan.shen@...iatek.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
DTML <devicetree@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
Seiya Wang <seiya.wang@...iatek.com>, wenst@...gle.com,
Project_Global_Chrome_Upstream_Group@...iatek.com,
Jitao Shi <jitao.shi@...iatek.com>
Subject: Re: [PATCH 22/27] arm64: dts: mt8195: add edp nodes
Hi, Tinghan:
Tinghan Shen <tinghan.shen@...iatek.com> 於 2021年6月16日 週三 上午5:35寫道：
>
> From: Jitao Shi <jitao.shi@...iatek.com>
>
> add edp nodes for mt8195
>
> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 59 +++++++++++++++++++++++-
> 1 file changed, 58 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 256818c4c0bf..d7d2c2a8f461 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -23,6 +23,8 @@
>
> aliases {
> dpi1 = &disp_dpi1;
> + dp-intf0 = &dp_intf0;
> + dp-intf1 = &dp_intf1;
> };
>
> clocks {
> @@ -1155,6 +1157,29 @@
> status = "disabled";
> };
>
> + disp_pwm0: disp_pwm0@...0e000 {
> + compatible = "mediatek,mt8183-disp-pwm";
You should use
compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
and add definition of "mediatek,mt8195-disp-pwm" in binding document.
> + reg = <0 0x1100e000 0 0x1000>;
> + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>,
> + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> + disp_pwm1: disp_pwm1@...0f000 {
> + compatible = "mediatek,mt8183-disp-pwm";
Ditto.
> + reg = <0 0x1100f000 0 0x1000>;
> + interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>,
> + <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> spi1: spi@...10000 {
> compatible = "mediatek,mt8195-spi",
> "mediatek,mt6765-spi";
> @@ -2397,6 +2422,30 @@
> status = "disabled";
> };
>
> + dp_intf1: dp_intf1@...13000 {
> + compatible = "mediatek,mt8195-dp-intf";
Where is the definition of this compatible?
> + reg = <0 0x1c113000 0 0x1000>;
> + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
> + <&vdosys1 CLK_VDO1_DPINTF>,
> + <&topckgen CLK_TOP_DP_SEL>,
> + <&topckgen CLK_TOP_TVDPLL2_D2>,
> + <&topckgen CLK_TOP_TVDPLL2_D4>,
> + <&topckgen CLK_TOP_TVDPLL2_D8>,
> + <&topckgen CLK_TOP_TVDPLL2_D16>,
> + <&topckgen CLK_TOP_TVDPLL2>;
> + clock-names = "hf_fmm_ck",
> + "hf_fdp_ck",
> + "MUX_DP",
> + "TVDPLL_D2",
> + "TVDPLL_D4",
> + "TVDPLL_D8",
> + "TVDPLL_D16",
> + "DPI_CK";
> + status = "disabled";
> + };
> +
> hdmi0: hdmi@...00000 {
> compatible = "mediatek,mt8195-hdmi";
> reg = <0 0x1c300000 0 0x1000>;
> @@ -2421,11 +2470,19 @@
>
> edp_tx: edp_tx@...00000 {
> status = "disabled";
> - compatible = "mediatek,mt8195-dp_tx";
> + compatible = "mediatek,mt8195-edp_tx";
> reg = <0 0x1c500000 0 0x8000>;
> power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
> interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
> };
> +
> + dp_tx: dp_tx@...00000 {
> + compatible = "mediatek,mt8195-dp_tx";
Ditto.
Regards,
Chun-Kuang.
> + reg = <0 0x1c600000 0 0x8000>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
> + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
> + status = "disabled";
> + };
> };
>
> hdmiddc0: ddc_i2c {
> --
> 2.18.0
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