linux-kernel - Re: [RFC PATCH v3 2/2] riscv: pgtable: Add "PBMT" extension supported

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Message-ID: <CAJF2gTT8BFyCNP4OtAaQLDYCPH+v5w5o3u02g9pQbBaE=kA_mw@mail.gmail.com>
Date:   Tue, 15 Jun 2021 17:28:27 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Anup Patel <anup@...infault.org>
Cc:     Anup Patel <anup.patel@....com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>,
        Arnd Bergmann <arnd@...db.de>, Chen-Yu Tsai <wens@...e.org>,
        Maxime Ripard <maxime@...no.tech>,
        Drew Fustini <drew@...gleboard.org>,
        liush <liush@...winnertech.com>,
        Wei Wu (吴伟) <lazyparser@...il.com>,
        wefu@...hat.com, linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        linux-sunxi@...ts.linux.dev, Guo Ren <guoren@...ux.alibaba.com>,
        Christoph Hellwig <hch@....de>,
        Daniel Lustig <dlustig@...dia.com>,
        Greg Favor <gfavor@...tanamicro.com>,
        Andrea Mondelli <andrea.mondelli@...wei.com>,
        Jonathan Behrens <behrensj@....edu>,
        Xinhaoqu <xinhaoqu@...wei.com>,
        Bill Huffman <huffman@...ence.com>,
        Nick Kossifidis <mick@....forth.gr>,
        Allen Baum <allen.baum@...erantotech.com>,
        Josh Scheid <jscheid@...tanamicro.com>,
        Richard Trauben <rtrauben@...il.com>
Subject: Re: [RFC PATCH v3 2/2] riscv: pgtable: Add "PBMT" extension supported

On Tue, Jun 15, 2021 at 12:11 PM Anup Patel <anup@...infault.org> wrote:
>
> On Mon, Jun 14, 2021 at 11:22 PM <guoren@...nel.org> wrote:
> >
> > From: Guo Ren <guoren@...ux.alibaba.com>
> >
> > "PBMT" - Page-Based Memory Types (see Link for detail), current it
> > has defined 3 memory types [62:61] in PTE:
> >  - WB 00 "Cacheable 'main memory'"
> >  - NC 01 "Noncacheable 'main memory'"
> >  - IO 11 "Non-cacheable non-idempotent 'I/O'"
> >
> > The patch not only implements the current PBMT extension but also
> > considers future scalability. It uses 3 words of image header to
> > store 8 memory types' values plus a mask value. That means there
> > are still 5 memory types reserved for future scalability.
>
> This is the worst work-around to the Linux RISC-V patch acceptance
> policy.
>
> Passing PTE attributes in the Linux Image header means boot-loaders
> will have to update the image header before jumping to Linux kernel.
> Basically, this is changing the Linux boot-process by adding platform
> specific image header updation step.
>
> Further, this patch is doing too many things in one-go. I needs to be
> broken down into smaller fine-grained patches.
Next time, I'll separate it into below patches:
 - riscv: pgtable: Fixup _PAGE_CHG_MASK usage
 - riscv: pgtable: Add "PBMT" extension supported
 - riscv: pgtable: Add vendor custom "PBMT" definitions interface
How?

>
> I totally disapprove of this patch in it's current shape since the
> Linux boot-protocol should not have any platform specific part.
I think you mean we shouldn't modify the uImage header.

How about parsing dtb before setup_vm (It's a very early stage before
mmu enabled)?  eg:
        cpus {
                ...
                rv64-pbmt-extension;
                rv64-pbmt-custom-remapping = <[mask] [type0] [type1] [type2]>;

>
> Also, please don't CC RVI mailing list for Linux patches because
> the people can post to RVI mailing list only by joining it.
Okay, I'll remove the RVI mailing list. If I needed to, I would send a
notification email to RVI separately.

--
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/