linux-kernel - Re: [PATCH V1] arm64: dts: qcom: sc7180: Added xo clock for eMMC and Sd card

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <f24b5538fb28595ab1d9353a6a8e429d@codeaurora.org>
Date:   Tue, 15 Jun 2021 15:30:07 +0530
From:   sbhanu@...eaurora.org
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     adrian.hunter@...el.com, ulf.hansson@...aro.org,
        robh+dt@...nel.org, asutoshd@...eaurora.org,
        stummala@...eaurora.org, vbadigan@...eaurora.org,
        rampraka@...eaurora.org, sayalil@...eaurora.org,
        sartgarg@...eaurora.org, rnayak@...eaurora.org,
        saiprakash.ranjan@...eaurora.org, sibis@...eaurora.org,
        okukatla@...eaurora.org, djakov@...nel.org, cang@...eaurora.org,
        pragalla@...eaurora.org, nitirawa@...eaurora.org,
        linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        agross@...nel.org
Subject: Re: [PATCH V1] arm64: dts: qcom: sc7180: Added xo clock for eMMC and
 Sd card

On 2021-06-14 22:00, Bjorn Andersson wrote:
> On Mon 14 Jun 06:55 CDT 2021, sbhanu@...eaurora.org wrote:
> 
>> On 2021-06-11 10:00, Bjorn Andersson wrote:
>> > On Thu 10 Jun 02:11 CDT 2021, Shaik Sajida Bhanu wrote:
>> >
>> > > Added xo clock for eMMC and Sd card.
>> >
>> > Was about to push out my branch of patches, but before I do. Can you
>> > please describe WHY this is needed?
>> >
>> > Regards,
>> > Bjorn
>> 
>> We are making use of this clock in dll register value calculation,
>> The default PoR value is also same as calculated value for
>> HS200/HS400/SDR104 modes.
>> But just not to rely on default register values we need this entry.
>> 
> 
> That is the perfect thing to include in a commit message!
> 
> I rewrote yours and applied the change, but please next time do 
> describe
> the "why" of your change.
> 
> Regards,
> Bjorn
Sure
> 
>> >
>> > >
>> > > Signed-off-by: Shaik Sajida Bhanu <sbhanu@...eaurora.org>
>> > > ---
>> > >  arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++----
>> > >  1 file changed, 6 insertions(+), 4 deletions(-)
>> > >
>> > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> > > b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> > > index 295844e..5bb6bd4 100644
>> > > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> > > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> > > @@ -701,8 +701,9 @@
>> > >  			interrupt-names = "hc_irq", "pwr_irq";
>> > >
>> > >  			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
>> > > -					<&gcc GCC_SDCC1_AHB_CLK>;
>> > > -			clock-names = "core", "iface";
>> > > +					<&gcc GCC_SDCC1_AHB_CLK>,
>> > > +					<&rpmhcc RPMH_CXO_CLK>;
>> > > +			clock-names = "core", "iface","xo";
>> > >  			interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
>> > >  					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
>> > >  			interconnect-names = "sdhc-ddr","cpu-sdhc";
>> > > @@ -2666,8 +2667,9 @@
>> > >  			interrupt-names = "hc_irq", "pwr_irq";
>> > >
>> > >  			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
>> > > -					<&gcc GCC_SDCC2_AHB_CLK>;
>> > > -			clock-names = "core", "iface";
>> > > +					<&gcc GCC_SDCC2_AHB_CLK>,
>> > > +					<&rpmhcc RPMH_CXO_CLK>;
>> > > +			clock-names = "core", "iface", "xo";
>> > >
>> > >  			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1
>> > > 0>,
>> > >  					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
>> > > --
>> > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
>> > > member
>> > > of Code Aurora Forum, hosted by The Linux Foundation
>> > >