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Message-ID: <20210616011551.29654-2-chun-jie.chen@mediatek.com>
Date: Wed, 16 Jun 2021 09:15:50 +0800
From: Chun-Jie Chen <chun-jie.chen@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Weiyi Lu <weiyi.lu@...iatek.com>,
Chun-Jie Chen <chun-jie.chen@...iatek.com>
Subject: [PATCH v4 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
Add clock controller nodes for SoC mt8192
Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9757138a8bbd..83f71d13ef9d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -257,6 +258,24 @@
};
};
+ topckgen: syscon@...00000 {
+ compatible = "mediatek,mt8192-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@...01000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@...03000 {
+ compatible = "mediatek,mt8192-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@...05000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -282,6 +301,12 @@
#interrupt-cells = <2>;
};
+ apmixedsys: syscon@...0c000 {
+ compatible = "mediatek,mt8192-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
systimer: timer@...17000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
@@ -291,6 +316,12 @@
clock-names = "clk13m";
};
+ scp_adsp: clock-controller@...20000 {
+ compatible = "mediatek,mt8192-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial@...02000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
@@ -311,6 +342,12 @@
status = "disabled";
};
+ imp_iic_wrap_c: clock-controller@...07000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_c";
+ reg = <0 0x11007000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
spi0: spi@...0a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@@ -436,6 +473,12 @@
status = "disable";
};
+ audsys: clock-controller@...10000 {
+ compatible = "mediatek,mt8192-audsys";
+ reg = <0 0x11210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c3: i2c3@...b0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
@@ -449,6 +492,12 @@
status = "disabled";
};
+ imp_iic_wrap_e: clock-controller@...b1000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_e";
+ reg = <0 0x11cb1000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c7: i2c7@...00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
@@ -488,6 +537,12 @@
status = "disabled";
};
+ imp_iic_wrap_s: clock-controller@...03000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c1: i2c1@...20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
@@ -527,6 +582,12 @@
status = "disabled";
};
+ imp_iic_wrap_ws: clock-controller@...23000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_ws";
+ reg = <0 0x11d23000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c5: i2c5@...00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
@@ -540,6 +601,12 @@
status = "disabled";
};
+ imp_iic_wrap_w: clock-controller@...01000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_w";
+ reg = <0 0x11e01000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c0: i2c0@...00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@@ -565,5 +632,101 @@
#size-cells = <0>;
status = "disabled";
};
+
+ imp_iic_wrap_n: clock-controller@...02000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_n";
+ reg = <0 0x11f02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc_top: clock-controller@...10000 {
+ compatible = "mediatek,mt8192-msdc_top";
+ reg = <0 0x11f10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc: clock-controller@...60000 {
+ compatible = "mediatek,mt8192-msdc";
+ reg = <0 0x11f60000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: clock-controller@...bf000 {
+ compatible = "mediatek,mt8192-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: clock-controller@...00000 {
+ compatible = "mediatek,mt8192-mmsys";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@...20000 {
+ compatible = "mediatek,mt8192-imgsys";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys2: clock-controller@...20000 {
+ compatible = "mediatek,mt8192-imgsys2";
+ reg = <0 0x15820000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@...0f000 {
+ compatible = "mediatek,mt8192-vdecsys_soc";
+ reg = <0 0x1600f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@...2f000 {
+ compatible = "mediatek,mt8192-vdecsys";
+ reg = <0 0x1602f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@...00000 {
+ compatible = "mediatek,mt8192-vencsys";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@...00000 {
+ compatible = "mediatek,mt8192-camsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@...4f000 {
+ compatible = "mediatek,mt8192-camsys_rawa";
+ reg = <0 0x1a04f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@...6f000 {
+ compatible = "mediatek,mt8192-camsys_rawb";
+ reg = <0 0x1a06f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawc: clock-controller@...8f000 {
+ compatible = "mediatek,mt8192-camsys_rawc";
+ reg = <0 0x1a08f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@...00000 {
+ compatible = "mediatek,mt8192-ipesys";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mdpsys: clock-controller@...00000 {
+ compatible = "mediatek,mt8192-mdpsys";
+ reg = <0 0x1f000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.18.0
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