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Message-ID: <CAFBinCB6bHy6Han0+oUcuGfccv1Rh_P0Gows1ezWdV4eA267tg@mail.gmail.com>
Date: Fri, 18 Jun 2021 14:11:58 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Artem Lapkin <email2tema@...il.com>
Cc: Neil Armstrong <narmstrong@...libre.com>, yue.wang@...ogic.com,
khilman@...libre.com, lorenzo.pieralisi@....com, robh@...nel.org,
kw@...ux.com, jbrunet@...libre.com, christianshewitt@...il.com,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
art@...das.com, nick@...das.com, gouwa@...das.com
Subject: Re: [PATCH] PCI: dwc: meson add quirk
Hi Artem,
On Fri, Jun 18, 2021 at 8:38 AM Artem Lapkin <email2tema@...il.com> wrote:
>
> Device set same 256 bytes maximum read request size equal MAX_READ_REQ_SIZE
> was find some issue with HDMI scrambled picture and nvme devices
> at intensive writing...
>
> [ 4.798971] nvme 0000:01:00.0: fix MRRS from 512 to 256
>
> This quirk setup same MRRS if we try solve this problem with
> pci=pcie_bus_perf kernel command line param
thank you for investigating this issue and for providing a fix!
[...]
> +static void meson_pcie_quirk(struct pci_dev *dev)
> +{
> + int mrrs;
> +
> + /* no need quirk */
> + if (pcie_bus_config != PCIE_BUS_DEFAULT)
> + return;
> +
> + /* no need for root bus */
> + if (pci_is_root_bus(dev->bus))
> + return;
> +
> + mrrs = pcie_get_readrq(dev);
> +
> + /*
> + * set same 256 bytes maximum read request size equal MAX_READ_REQ_SIZE
> + * was find some issue with HDMI scrambled picture and nvme devices
> + * at intensive writing...
> + */
> +
> + if (mrrs != MAX_READ_REQ_SIZE) {
> + dev_info(&dev->dev, "fix MRRS from %d to %d\n", mrrs, MAX_READ_REQ_SIZE);
> + pcie_set_readrq(dev, MAX_READ_REQ_SIZE);
> + }
> +}
> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, meson_pcie_quirk);
it seems that other PCIe controllers need something similar. in
particular I found pci-keystone [0] and pci-loongson [1]
while comparing your code with the two existing implementations two
things came to my mind:
1. your implementation slightly differs from the two existing ones as
it's not walking through the parent PCI busses (I think this would be
relevant if there's another bridge between the host bridge and the
actual device)
2. (this is a question towards the PCI maintainers) does it make sense
to have this MRRS quirk re-usable somewhere?
Best regards,
Martin
[0] https://elixir.bootlin.com/linux/v5.12/source/drivers/pci/controller/dwc/pci-keystone.c#L524
[1] https://elixir.bootlin.com/linux/v5.12/source/drivers/pci/controller/pci-loongson.c#L63
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